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e0d29d4ada
PMS aware chips require prefetch padding size for instruction fetch, or some memory alignment considerations. These settings are now exposed through kconfig options (hidden) and used through common ld template. This shall help to add and manage future chips support easily for these considerations. Closes IDF-3624
25 lines
707 B
Plaintext
25 lines
707 B
Plaintext
/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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/* CPU instruction prefetch padding size for flash mmap scenario */
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_esp_flash_mmap_prefetch_pad_size = 16;
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/* CPU instruction prefetch padding size for memory protection scenario */
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#ifdef CONFIG_ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE
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_esp_memprot_prefetch_pad_size = CONFIG_ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE;
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#else
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_esp_memprot_prefetch_pad_size = 0;
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#endif
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/* Memory alignment size for PMS */
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#ifdef CONFIG_ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE
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_esp_memprot_align_size = CONFIG_ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE;
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#else
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_esp_memprot_align_size = 0;
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#endif
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