esp-idf/components/esp_system/port/soc/esp32c3
Gustavo Henrique Nihei 3cbac3dd1d esp_system: Ensure TIMG0 clock is always enabled during normal operation
If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
registers (Flashboot protection included) will be re-enabled, and some
seconds later, will trigger an unintended reset.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-06 04:58:11 +00:00
..
apb_backup_dma.c esp_wifi: fix esp32c3 code issues 2021-01-10 16:16:28 +08:00
cache_err_int.c bugfix: esprv_intc_int_set_type() should not use bitmap parameter 2022-10-14 11:31:22 +08:00
clk.c esp_system: Ensure TIMG0 clock is always enabled during normal operation 2023-03-06 04:58:11 +00:00
CMakeLists.txt debug_stubs: Refactor and add support for RISCV 2021-11-04 01:33:24 +03:00
Kconfig.cpu soc: moved kconfig options out of the target component. 2022-04-21 12:09:43 +08:00
Kconfig.system system: move kconfig options out of target component 2022-03-02 01:22:26 +00:00
reset_reason.c reset_reasons: EFUSE_RST is treated as POWERON_RST 2022-06-09 17:49:03 +08:00
system_internal.c usb_serial_jtag: Improve the code for the issue of usb cdc device unable to work during sleep 2023-02-27 12:10:49 +08:00