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124 lines
4.0 KiB
C
124 lines
4.0 KiB
C
// The long term plan is to have a single soc_caps.h for each peripheral.
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// During the refactoring and multichip support development process, we
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// seperate these information into periph_caps.h for each peripheral and
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// include them here.
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#pragma once
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#define SOC_CPU_CORES_NUM 1
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#define SOC_GDMA_SUPPORTED 1
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#define SOC_TWAI_SUPPORTED 1
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// There are 3 DMA channels on ESP32-C3
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// Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically
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// Remove them when GDMA driver API is ready
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#define SOC_GDMA_AES_DMA_CHANNEL (0)
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#define SOC_GDMA_SHA_DMA_CHANNEL (1)
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#define SOC_GDMA_SPI2_DMA_CHANNEL (2)
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#define SOC_GDMA_ADC_DMA_CHANNEL (0)
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//NOTE: The CHx number should be consistent with the selected DMA channel above
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#define SOC_GDMA_SPI2_INTR_SOURCE ETS_DMA_CH2_INTR_SOURCE
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//On C3, there is only 1 GPSPI controller (GPSPI2)
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#define SOC_GDMA_SPI3_DMA_CHANNEL SOC_GDMA_SPI2_DMA_CHANNEL
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#define SOC_GDMA_ADC_INTR_SOURCE ETS_DMA_CH0_INTR_SOURCE
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#include "rmt_caps.h"
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#include "dac_caps.h"
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#include "i2c_caps.h"
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#include "mpu_caps.h"
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#include "sigmadelta_caps.h"
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#include "systimer_caps.h"
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#include "uart_caps.h"
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#include "brownout_caps.h"
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#include "gdma_caps.h"
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#include "i2s_caps.h"
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#include "rtc_io_caps.h"
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#include "soc_caps.h"
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#include "timer_group_caps.h"
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#include "cpu_caps.h"
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#include "gpio_caps.h"
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#include "ledc_caps.h"
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#include "rmt_caps.h"
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#include "spi_caps.h"
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#include "uart_caps.h"
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/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
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#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */
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/*-------------------------- TWAI CAPS ---------------------------------------*/
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#define SOC_TWAI_BRP_MIN 2
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#define SOC_TWAI_BRP_MAX 32768
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#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
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#define SOC_ADC_MAX_CHANNEL_NUM (10)
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/**
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* Check if adc support digital controller (DMA) mode.
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* @value
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* - 1 : support;
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* - 0 : not support;
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*/
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#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1
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/*--------------------------- SHA CAPS ---------------------------------------*/
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/* Max amount of bytes in a single DMA operation is 4095,
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for SHA this means that the biggest safe amount of bytes is
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31 blocks of 128 bytes = 3968
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*/
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#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
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#define SOC_SHA_SUPPORT_DMA (1)
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/* The SHA engine is able to resume hashing from a user */
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#define SOC_SHA_SUPPORT_RESUME (1)
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/* Has a centralized DMA, which is shared with all peripherals */
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#define SOC_SHA_GENERAL_DMA (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA224 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (3072)
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/*-------------------------- AES CAPS -----------------------------------------*/
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#define SOC_AES_SUPPORT_DMA (1)
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/* Has a centralized DMA, which is shared with all peripherals */
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#define SOC_AES_GENERAL_DMA (1)
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#define SOC_AES_SUPPORT_AES_128 (1)
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#define SOC_AES_SUPPORT_AES_256 (1)
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/*-------------------------- ADC CAPS -------------------------------*/
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#define SOC_ADC_PERIPH_NUM (2)
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#define SOC_ADC_PATT_LEN_MAX (16)
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#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
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#define SOC_ADC_MAX_CHANNEL_NUM (10)
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/**
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* Check if adc support digital controller (DMA) mode.
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* @value
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* - 1 : support;
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* - 0 : not support;
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*/
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#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1
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/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
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#define SOC_APB_BACKUP_DMA (1)
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/*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/
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#define SOC_WIFI_HW_TSF (1)
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/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
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#define SOC_COEX_HW_PTI (1)
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