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https://github.com/espressif/esp-idf.git
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27a9cf861e
Some ESP32-C3 drivers are still pending. Based on internal commit 3ef01301fffa552d4be6d81bc9d199c223224305
42 lines
1.4 KiB
C
42 lines
1.4 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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// ESP32-C3 has 1 GPIO peripheral
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#define SOC_GPIO_PORT (1)
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#define SOC_GPIO_PIN_COUNT (22)
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// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
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// On ESP32-C3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
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#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
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// Force hold is a new function of ESP32-C3
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#define GPIO_SUPPORTS_FORCE_HOLD (1)
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#define GPIO_MODE_DEF_DISABLE (0)
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#define GPIO_MODE_DEF_INPUT (BIT0)
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#define GPIO_MODE_DEF_OUTPUT (BIT1)
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#define GPIO_MODE_DEF_OD (BIT2)
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#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
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#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
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#ifdef __cplusplus
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}
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#endif
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