esp-idf/components/ulp/ulp_riscv
Marius Vikhammer 7b5bdcf077 ulp-riscv: always force COCPU clock on S3
The coprocessor cpu trap signal doesnt have a stable reset value,
force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU
2022-10-18 03:06:05 +00:00
..
include ulp-fsm: Update ulp-fsm ADC example with S3 support 2022-09-07 16:48:06 +08:00
shared/include ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP. 2022-08-05 18:16:31 +08:00
ulp_core ulp: Added support for RTC I2C driver for ULP RISC-V on esp32s2 and esp32s3 2022-09-05 10:21:43 +02:00
ulp_riscv_i2c.c ulp: Added support for RTC I2C driver for ULP RISC-V on esp32s2 and esp32s3 2022-09-05 10:21:43 +02:00
ulp_riscv_lock.c ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP. 2022-08-05 18:16:31 +08:00
ulp_riscv.c ulp-riscv: always force COCPU clock on S3 2022-10-18 03:06:05 +00:00