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https://github.com/espressif/esp-idf.git
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36ccdee6ec
Without this, it's possible for stale information to be read from cache via mmap, even if the MMU table entry had been invalidated prior to writing flash (if the same MMU table entry was re-used after writing flash.)
210 lines
6.7 KiB
C
210 lines
6.7 KiB
C
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// Test for spi_flash_{read,write}.
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#include <assert.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <sys/param.h>
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#include <unity.h>
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#include <esp_spi_flash.h>
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#include <rom/spi_flash.h>
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#include "../cache_utils.h"
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#include "soc/timer_group_struct.h"
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#include "soc/timer_group_reg.h"
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#include "test_config.h"
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/* Base offset in flash for tests. */
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#define FLASH_BASE TEST_REGION_START
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#ifndef CONFIG_SPI_FLASH_MINIMAL_TEST
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#define CONFIG_SPI_FLASH_MINIMAL_TEST 1
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#endif
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static void fill(char *dest, int32_t start, int32_t len)
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{
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for (int32_t i = 0; i < len; i++) {
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*(dest + i) = (char) (start + i);
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}
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}
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static int cmp_or_dump(const void *a, const void *b, size_t len)
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{
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int r = memcmp(a, b, len);
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if (r != 0) {
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for (int i = 0; i < len; i++) {
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fprintf(stderr, "%02x", ((unsigned char *) a)[i]);
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}
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fprintf(stderr, "\n");
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for (int i = 0; i < len; i++) {
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fprintf(stderr, "%02x", ((unsigned char *) b)[i]);
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}
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fprintf(stderr, "\n");
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}
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return r;
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}
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static void IRAM_ATTR test_read(int src_off, int dst_off, int len)
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{
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uint32_t src_buf[16];
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char dst_buf[64], dst_gold[64];
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fprintf(stderr, "src=%d dst=%d len=%d\n", src_off, dst_off, len);
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memset(src_buf, 0xAA, sizeof(src_buf));
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fill(((char *) src_buf) + src_off, src_off, len);
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ESP_ERROR_CHECK(spi_flash_erase_sector((FLASH_BASE + src_off) / SPI_FLASH_SEC_SIZE));
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spi_flash_disable_interrupts_caches_and_other_cpu();
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SpiFlashOpResult rc = SPIWrite(FLASH_BASE, src_buf, sizeof(src_buf));
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spi_flash_enable_interrupts_caches_and_other_cpu();
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TEST_ASSERT_EQUAL_INT(rc, SPI_FLASH_RESULT_OK);
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memset(dst_buf, 0x55, sizeof(dst_buf));
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memset(dst_gold, 0x55, sizeof(dst_gold));
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fill(dst_gold + dst_off, src_off, len);
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ESP_ERROR_CHECK(spi_flash_read(FLASH_BASE + src_off, dst_buf + dst_off, len));
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TEST_ASSERT_EQUAL_INT(cmp_or_dump(dst_buf, dst_gold, sizeof(dst_buf)), 0);
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}
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TEST_CASE("Test spi_flash_read", "[spi_flash_read]")
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{
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#if CONFIG_SPI_FLASH_MINIMAL_TEST
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test_read(0, 0, 0);
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test_read(0, 0, 4);
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test_read(0, 0, 16);
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test_read(0, 0, 64);
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test_read(0, 0, 1);
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test_read(0, 1, 1);
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test_read(1, 0, 1);
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test_read(1, 1, 1);
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test_read(1, 1, 2);
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test_read(1, 1, 3);
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test_read(1, 1, 4);
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test_read(1, 1, 5);
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test_read(3, 2, 5);
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test_read(0, 0, 17);
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test_read(0, 1, 17);
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test_read(1, 0, 17);
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test_read(1, 1, 17);
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test_read(1, 1, 18);
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test_read(1, 1, 19);
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test_read(1, 1, 20);
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test_read(1, 1, 21);
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test_read(3, 2, 21);
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test_read(4, 4, 60);
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test_read(59, 0, 5);
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test_read(60, 0, 4);
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test_read(60, 0, 3);
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test_read(60, 0, 2);
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test_read(63, 0, 1);
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test_read(64, 0, 0);
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test_read(59, 59, 5);
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test_read(60, 60, 4);
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test_read(60, 60, 3);
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test_read(60, 60, 2);
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test_read(63, 63, 1);
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test_read(64, 64, 0);
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#else
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/* This will run a more thorough test but will slam flash pretty hard. */
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for (int src_off = 1; src_off < 16; src_off++) {
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for (int dst_off = 0; dst_off < 16; dst_off++) {
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for (int len = 0; len < 32; len++) {
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test_read(dst_off, src_off, len);
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}
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}
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}
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#endif
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}
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static void IRAM_ATTR test_write(int dst_off, int src_off, int len)
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{
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char src_buf[64], dst_gold[64];
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uint32_t dst_buf[16];
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fprintf(stderr, "dst=%d src=%d len=%d\n", dst_off, src_off, len);
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memset(src_buf, 0x55, sizeof(src_buf));
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fill(src_buf + src_off, src_off, len);
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// Fills with 0xff
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ESP_ERROR_CHECK(spi_flash_erase_sector((FLASH_BASE + dst_off) / SPI_FLASH_SEC_SIZE));
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memset(dst_gold, 0xff, sizeof(dst_gold));
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if (len > 0) {
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int pad_left_off = (dst_off & ~3U);
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memset(dst_gold + pad_left_off, 0xff, 4);
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if (dst_off + len > pad_left_off + 4 && (dst_off + len) % 4 != 0) {
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int pad_right_off = ((dst_off + len) & ~3U);
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memset(dst_gold + pad_right_off, 0xff, 4);
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}
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fill(dst_gold + dst_off, src_off, len);
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}
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ESP_ERROR_CHECK(spi_flash_write(FLASH_BASE + dst_off, src_buf + src_off, len));
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spi_flash_disable_interrupts_caches_and_other_cpu();
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SpiFlashOpResult rc = SPIRead(FLASH_BASE, dst_buf, sizeof(dst_buf));
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spi_flash_enable_interrupts_caches_and_other_cpu();
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TEST_ASSERT_EQUAL_INT(rc, SPI_FLASH_RESULT_OK);
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TEST_ASSERT_EQUAL_INT(cmp_or_dump(dst_buf, dst_gold, sizeof(dst_buf)), 0);
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}
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TEST_CASE("Test spi_flash_write", "[spi_flash_write]")
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{
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#if CONFIG_SPI_FLASH_MINIMAL_TEST
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test_write(0, 0, 0);
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test_write(0, 0, 4);
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test_write(0, 0, 16);
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test_write(0, 0, 64);
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test_write(0, 0, 1);
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test_write(0, 1, 1);
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test_write(1, 0, 1);
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test_write(1, 1, 1);
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test_write(1, 1, 2);
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test_write(1, 1, 3);
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test_write(1, 1, 4);
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test_write(1, 1, 5);
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test_write(3, 2, 5);
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test_write(4, 4, 60);
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test_write(59, 0, 5);
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test_write(60, 0, 4);
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test_write(60, 0, 3);
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test_write(60, 0, 2);
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test_write(63, 0, 1);
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test_write(64, 0, 0);
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test_write(59, 59, 5);
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test_write(60, 60, 4);
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test_write(60, 60, 3);
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test_write(60, 60, 2);
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test_write(63, 63, 1);
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test_write(64, 64, 0);
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#else
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/* This will run a more thorough test but will slam flash pretty hard. */
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for (int dst_off = 1; dst_off < 16; dst_off++) {
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for (int src_off = 0; src_off < 16; src_off++) {
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for (int len = 0; len < 16; len++) {
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test_write(dst_off, src_off, len);
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}
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}
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}
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#endif
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/*
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* Test writing from ROM, IRAM and caches. We don't know what exactly will be
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* written, we're testing that there's no crash here.
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*
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* NB: At the moment these only support aligned addresses, because memcpy
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* is not aware of the 32-but load requirements for these regions.
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*/
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ESP_ERROR_CHECK(spi_flash_write(FLASH_BASE, (char *) 0x40000000, 16));
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ESP_ERROR_CHECK(spi_flash_write(FLASH_BASE, (char *) 0x40070000, 16));
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ESP_ERROR_CHECK(spi_flash_write(FLASH_BASE, (char *) 0x40078000, 16));
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ESP_ERROR_CHECK(spi_flash_write(FLASH_BASE, (char *) 0x40080000, 16));
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}
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