mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
29accf2533
Note: on ESP32 UART rxfifo seems to be read as u8 instead of u32 to make it work
178 lines
5.4 KiB
C
178 lines
5.4 KiB
C
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_PCNT_STRUCT_H_
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#define _SOC_PCNT_STRUCT_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct pcnt_dev_s {
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struct {
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union {
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struct {
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uint32_t filter_thres: 10;
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uint32_t filter_en: 1;
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uint32_t thr_zero_en: 1;
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uint32_t thr_h_lim_en: 1;
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uint32_t thr_l_lim_en: 1;
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uint32_t thr_thres0_en: 1;
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uint32_t thr_thres1_en: 1;
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uint32_t ch0_neg_mode: 2;
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uint32_t ch0_pos_mode: 2;
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uint32_t ch0_hctrl_mode: 2;
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uint32_t ch0_lctrl_mode: 2;
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uint32_t ch1_neg_mode: 2;
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uint32_t ch1_pos_mode: 2;
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uint32_t ch1_hctrl_mode: 2;
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uint32_t ch1_lctrl_mode: 2;
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};
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uint32_t val;
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} conf0;
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union {
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struct {
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uint32_t cnt_thres0: 16;
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uint32_t cnt_thres1: 16;
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};
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uint32_t val;
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} conf1;
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union {
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struct {
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uint32_t cnt_h_lim: 16;
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uint32_t cnt_l_lim: 16;
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};
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uint32_t val;
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} conf2;
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} conf_unit[4];
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union {
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struct {
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uint32_t cnt_val: 16;
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uint32_t reserved16: 16;
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};
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uint32_t val;
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} cnt_unit[4];
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union {
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struct {
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uint32_t cnt_thr_event_u0: 1;
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uint32_t cnt_thr_event_u1: 1;
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uint32_t cnt_thr_event_u2: 1;
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uint32_t cnt_thr_event_u3: 1;
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uint32_t reserved4: 28;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t cnt_thr_event_u0: 1;
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uint32_t cnt_thr_event_u1: 1;
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uint32_t cnt_thr_event_u2: 1;
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uint32_t cnt_thr_event_u3: 1;
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uint32_t reserved4: 28;
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};
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uint32_t val;
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} int_st;
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union {
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struct {
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uint32_t cnt_thr_event_u0: 1;
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uint32_t cnt_thr_event_u1: 1;
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uint32_t cnt_thr_event_u2: 1;
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uint32_t cnt_thr_event_u3: 1;
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uint32_t reserved4: 28;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t cnt_thr_event_u0: 1;
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uint32_t cnt_thr_event_u1: 1;
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uint32_t cnt_thr_event_u2: 1;
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uint32_t cnt_thr_event_u3: 1;
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uint32_t reserved4: 28;
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t cnt_mode: 2;
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uint32_t thres1_lat: 1;
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uint32_t thres0_lat: 1;
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uint32_t l_lim_lat: 1;
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uint32_t h_lim_lat: 1;
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uint32_t zero_lat: 1;
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uint32_t reserved7: 25;
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};
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uint32_t val;
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} status_unit[4];
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union {
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struct {
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uint32_t cnt_rst_u0: 1;
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uint32_t cnt_pause_u0: 1;
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uint32_t cnt_rst_u1: 1;
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uint32_t cnt_pause_u1: 1;
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uint32_t cnt_rst_u2: 1;
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uint32_t cnt_pause_u2: 1;
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uint32_t cnt_rst_u3: 1;
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uint32_t cnt_pause_u3: 1;
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uint32_t reserved8: 8;
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uint32_t clk_en: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} ctrl;
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uint32_t reserved_64;
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uint32_t reserved_68;
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uint32_t reserved_6c;
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uint32_t reserved_70;
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uint32_t reserved_74;
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uint32_t reserved_78;
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uint32_t reserved_7c;
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uint32_t reserved_80;
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uint32_t reserved_84;
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uint32_t reserved_88;
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uint32_t reserved_8c;
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uint32_t reserved_90;
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uint32_t reserved_94;
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uint32_t reserved_98;
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uint32_t reserved_9c;
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uint32_t reserved_a0;
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uint32_t reserved_a4;
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uint32_t reserved_a8;
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uint32_t reserved_ac;
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uint32_t reserved_b0;
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uint32_t reserved_b4;
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uint32_t reserved_b8;
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uint32_t reserved_bc;
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uint32_t reserved_c0;
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uint32_t reserved_c4;
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uint32_t reserved_c8;
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uint32_t reserved_cc;
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uint32_t reserved_d0;
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uint32_t reserved_d4;
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uint32_t reserved_d8;
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uint32_t reserved_dc;
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uint32_t reserved_e0;
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uint32_t reserved_e4;
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uint32_t reserved_e8;
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uint32_t reserved_ec;
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uint32_t reserved_f0;
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uint32_t reserved_f4;
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uint32_t reserved_f8;
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uint32_t date; /**/
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} pcnt_dev_t;
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extern pcnt_dev_t PCNT;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_PCNT_STRUCT_H_ */
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