Armando c331c85318 mspi: make cpu clock source switch safe ... For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required. Certain delays will be added to the MSPI RX direction. When system clock switches down, the delays should be cleared. When system clock switches up, the delays should be restored.		2021-10-19 21:47:27 +08:00
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esp32	esp_hw_support: force power down wifi and bt power domain when rtc module init	2021-10-14 10:51:10 +08:00
esp32c3	fix rtc_clk_cal: Wait for timeout in a loop instead of just judge once	2021-10-19 12:07:34 +08:00
esp32h2	fix rtc_clk_cal: Wait for timeout in a loop instead of just judge once	2021-10-19 12:07:34 +08:00
esp32s2	fix rtc_clk_cal: Wait for timeout in a loop instead of just judge once	2021-10-19 12:07:34 +08:00
esp32s3	mspi: make cpu clock source switch safe	2021-10-19 21:47:27 +08:00
include	esp_hw_support: update copyright notice 3	2021-08-10 13:30:57 +02:00
async_memcpy_impl_gdma.c	esp_hw_support: update copyright notice 3	2021-08-10 13:30:57 +02:00