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https://github.com/espressif/esp-idf.git
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132 lines
6.5 KiB
C
132 lines
6.5 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include "soc/soc.h"
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#include "soc/sensitive_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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//IRAM0 interrupt status bitmasks
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#define IRAM0_INTR_ST_OP_TYPE_BIT BIT(1) //instruction: 0, data: 1
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#define IRAM0_INTR_ST_OP_RW_BIT BIT(0) //read: 0, write: 1
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#define CONF_REG_ADDRESS_SHIFT 2
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//IRAM0 range
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#define IRAM0_SRAM_BASE_ADDRESS 0x40000000
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#define IRAM0_SRAM_ADDRESS_LOW 0x40020000
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#define IRAM0_SRAM_ADDRESS_HIGH 0x4006FFFF
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//IRAM0 unified managemnt blocks
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#define IRAM0_SRAM_TOTAL_UNI_BLOCKS 4
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#define IRAM0_SRAM_UNI_BLOCK_0 0
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#define IRAM0_SRAM_UNI_BLOCK_1 1
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#define IRAM0_SRAM_UNI_BLOCK_2 2
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#define IRAM0_SRAM_UNI_BLOCK_3 3
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//unified management addr range (blocks 0-3)
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#define IRAM0_SRAM_UNI_BLOCK_0_LOW 0x40020000
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#define IRAM0_SRAM_UNI_BLOCK_1_LOW 0x40022000
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#define IRAM0_SRAM_UNI_BLOCK_2_LOW 0x40024000
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#define IRAM0_SRAM_UNI_BLOCK_3_LOW 0x40026000
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//split management addr range (blocks 4-21)
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#define IRAM0_SRAM_SPL_BLOCK_LOW 0x40028000 //block 4 low
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#define IRAM0_SRAM_SPL_BLOCK_HIGH 0x4006FFFF //block 21 high
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#define IRAM0_INTR_ST_FAULTADDR_M 0x003FFFFC //bits 21:6 in the reg, as well as in real address
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#define IRAM0_SRAM_INTR_ST_FAULTADDR_HI 0x40000000 //high nonsignificant bits 31:22 of the faulting address - constant
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#define IRAM0_SRAM_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR) << DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_S)
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//IRAM0 RTCFAST
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#define IRAM0_RTCFAST_ADDRESS_LOW 0x40070000
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#define IRAM0_RTCFAST_ADDRESS_HIGH 0x40071FFF
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#define IRAM0_RTCFAST_INTR_ST_FAULTADDR_HI 0x40070000 //RTCFAST faulting address high bits (31:22, constant)
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#define IRAM0_RTCFAST_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR) << DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_S)
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//DRAM0 interrupt status bitmasks
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#define DRAM0_INTR_ST_FAULTADDR_M 0x03FFFFC0 //(bits 25:6 in the reg)
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#define DRAM0_INTR_ST_FAULTADDR_S 0x4 //(bits 21:2 of real address)
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#define DRAM0_INTR_ST_OP_RW_BIT BIT(4) //read: 0, write: 1
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#define DRAM0_INTR_ST_OP_ATOMIC_BIT BIT(5) //non-atomic: 0, atomic: 1
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#define DRAM0_SRAM_ADDRESS_LOW 0x3FFB0000
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#define DRAM0_SRAM_ADDRESS_HIGH 0x3FFFFFFF
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#define DRAM0_SRAM_TOTAL_UNI_BLOCKS 4
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#define DRAM0_SRAM_UNI_BLOCK_0 0
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#define DRAM0_SRAM_UNI_BLOCK_1 1
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#define DRAM0_SRAM_UNI_BLOCK_2 2
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#define DRAM0_SRAM_UNI_BLOCK_3 3
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//unified management (SRAM blocks 0-3)
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#define DRAM0_SRAM_UNI_BLOCK_0_LOW 0x3FFB0000
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#define DRAM0_SRAM_UNI_BLOCK_1_LOW 0x3FFB2000
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#define DRAM0_SRAM_UNI_BLOCK_2_LOW 0x3FFB4000
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#define DRAM0_SRAM_UNI_BLOCK_3_LOW 0x3FFB6000
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//split management (SRAM blocks 4-21)
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#define DRAM0_SRAM_SPL_BLOCK_HIGH 0x3FFFFFFF //block 21 high
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#define DRAM0_SRAM_INTR_ST_FAULTADDR_HI 0x3FF00000 //SRAM high bits 31:22 of the faulting address - constant
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#define DRAM0_SRAM_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR) << DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_S)
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//DRAM0 RTCFAST
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#define DRAM0_RTCFAST_ADDRESS_LOW 0x3FF9E000
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#define DRAM0_RTCFAST_ADDRESS_HIGH 0x3FF9FFFF
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#define DRAM0_RTCFAST_INTR_ST_FAULTADDR_HI 0x3FF00000 //RTCFAST high bits 31:22 of the faulting address - constant
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#define DRAM0_RTCFAST_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR) << DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_S)
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//RTCSLOW
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#define RTCSLOW_MEMORY_SIZE 0x00002000
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//PeriBus1 interrupt status bitmasks
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#define PERI1_INTR_ST_OP_TYPE_BIT BIT(4) //0: non-atomic, 1: atomic
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#define PERI1_INTR_ST_OP_HIGH_BITS BIT(5) //0: high bits = unchanged, 1: high bits = 0x03F40000
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#define PERI1_INTR_ST_FAULTADDR_M 0x03FFFFC0 //(bits 25:6 in the reg)
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#define PERI1_INTR_ST_FAULTADDR_S 0x4 //(bits 21:2 of real address)
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#define PERI1_RTCSLOW_ADDRESS_BASE 0x3F421000
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#define PERI1_RTCSLOW_ADDRESS_LOW PERI1_RTCSLOW_ADDRESS_BASE
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#define PERI1_RTCSLOW_ADDRESS_HIGH PERI1_RTCSLOW_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE
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#define PERI1_RTCSLOW_INTR_ST_FAULTADDR_HI_0 0x3F400000
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#define PERI1_RTCSLOW_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR) << DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_S)
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//PeriBus2 interrupt status bitmasks
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#define PERI2_INTR_ST_OP_TYPE_BIT BIT(1) //instruction: 0, data: 1
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#define PERI2_INTR_ST_OP_RW_BIT BIT(0) //read: 0, write: 1
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#define PERI2_INTR_ST_FAULTADDR_M 0xFFFFFFFC //(bits 31:2 in the reg)
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#define PERI2_RTCSLOW_0_ADDRESS_BASE 0x50000000
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#define PERI2_RTCSLOW_0_ADDRESS_LOW PERI2_RTCSLOW_0_ADDRESS_BASE
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#define PERI2_RTCSLOW_0_ADDRESS_HIGH PERI2_RTCSLOW_0_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE
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#define PERI2_RTCSLOW_0_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR) << DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_S)
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#define PERI2_RTCSLOW_1_ADDRESS_BASE 0x60021000
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#define PERI2_RTCSLOW_1_ADDRESS_LOW PERI2_RTCSLOW_1_ADDRESS_BASE
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#define PERI2_RTCSLOW_1_ADDRESS_HIGH PERI2_RTCSLOW_1_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE
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#define PERI2_RTCSLOW_1_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR) << DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_S)
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#ifdef __cplusplus
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}
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#endif
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