mirror of
https://github.com/espressif/esp-idf.git
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585 lines
18 KiB
C
585 lines
18 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Region filter enable register */
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/** Type of region_filter_en register
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* Region filter enable register
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*/
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typedef union {
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struct {
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/** region_filter_en : R/W; bitpos: [15:0]; default: 1;
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* Configure bit $n (0-15) to enable region $n.\\
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* 0: disable \\
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* 1: enable \\
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*/
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uint32_t region_filter_en:16;
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uint32_t reserved_16:16;
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};
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uint32_t val;
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} hp_apm_region_filter_en_reg_t;
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/** Group: Region address register */
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/** Type of regionn_addr_start register
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* Region address register
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*/
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typedef union {
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struct {
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/** regionn_addr_start : R/W; bitpos: [31:0]; default: 0;
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* Configures start address of region n.
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*/
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uint32_t regionn_addr_start:32;
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};
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uint32_t val;
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} hp_apm_regionn_addr_start_reg_t;
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/** Type of regionn_addr_end register
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* Region address register
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*/
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typedef union {
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struct {
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/** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
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* Configures end address of region n.
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*/
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uint32_t regionn_addr_end:32;
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};
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uint32_t val;
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} hp_apm_regionn_addr_end_reg_t;
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/** Group: Region access authority attribute register */
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/** Type of regionn_attr register
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* Region access authority attribute register
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*/
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typedef union {
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struct {
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/** regionn_r0_x : R/W; bitpos: [0]; default: 0;
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* Configures the execution authority of REE_MODE 0 in region n.
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*/
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uint32_t regionn_r0_x:1;
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/** regionn_r0_w : R/W; bitpos: [1]; default: 0;
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* Configures the write authority of REE_MODE 0 in region n.
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*/
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uint32_t regionn_r0_w:1;
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/** regionn_r0_r : R/W; bitpos: [2]; default: 0;
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* Configures the read authority of REE_MODE 0 in region n.
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*/
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uint32_t regionn_r0_r:1;
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uint32_t reserved_3:1;
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/** regionn_r1_x : R/W; bitpos: [4]; default: 0;
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* Configures the execution authority of REE_MODE 1 in region n.
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*/
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uint32_t regionn_r1_x:1;
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/** regionn_r1_w : R/W; bitpos: [5]; default: 0;
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* Configures the write authority of REE_MODE 1 in region n.
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*/
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uint32_t regionn_r1_w:1;
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/** regionn_r1_r : R/W; bitpos: [6]; default: 0;
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* Configures the read authority of REE_MODE 1 in region n.
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*/
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uint32_t regionn_r1_r:1;
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uint32_t reserved_7:1;
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/** regionn_r2_x : R/W; bitpos: [8]; default: 0;
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* Configures the execution authority of REE_MODE 2 in region n.
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*/
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uint32_t regionn_r2_x:1;
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/** regionn_r2_w : R/W; bitpos: [9]; default: 0;
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* Configures the write authority of REE_MODE 2 in region n.
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*/
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uint32_t regionn_r2_w:1;
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/** regionn_r2_r : R/W; bitpos: [10]; default: 0;
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* Configures the read authority of REE_MODE 2 in region n.
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*/
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uint32_t regionn_r2_r:1;
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/** regionn_lock : R/W; bitpos: [11]; default: 0;
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* Set 1 to lock region0 configuration
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*/
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uint32_t regionn_lock:1;
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uint32_t reserved_12:20;
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};
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uint32_t val;
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} hp_apm_regionn_attr_reg_t;
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/** Group: function control register */
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/** Type of func_ctrl register
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* APM function control register
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*/
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typedef union {
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struct {
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/** m0_func_en : R/W; bitpos: [0]; default: 1;
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* PMS M0 function enable
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*/
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uint32_t m0_func_en:1;
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/** m1_func_en : R/W; bitpos: [1]; default: 1;
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* PMS M1 function enable
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*/
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uint32_t m1_func_en:1;
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/** m2_func_en : R/W; bitpos: [2]; default: 1;
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* PMS M2 function enable
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*/
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uint32_t m2_func_en:1;
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/** m3_func_en : R/W; bitpos: [3]; default: 1;
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* PMS M3 function enable
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*/
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uint32_t m3_func_en:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} hp_apm_func_ctrl_reg_t;
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/** Group: M0 status register */
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/** Type of m0_status register
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* M0 status register
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*/
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typedef union {
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struct {
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/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
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* Represents exception status.\\
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* bit0: 1 represents authority_exception \\
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* bit1: 1 represents space_exception \\
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*/
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uint32_t m0_exception_status:2;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} hp_apm_m0_status_reg_t;
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/** Group: M0 status clear register */
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/** Type of m0_status_clr register
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* M0 status clear register
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*/
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typedef union {
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struct {
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/** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
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* Configures to clear exception status.
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*/
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uint32_t m0_exception_status_clr:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} hp_apm_m0_status_clr_reg_t;
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/** Group: M0 exception_info0 register */
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/** Type of m0_exception_info0 register
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* M0 exception_info0 register
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*/
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typedef union {
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struct {
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/** m0_exception_region : RO; bitpos: [15:0]; default: 0;
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* Represents exception region.
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*/
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uint32_t m0_exception_region:16;
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/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
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* Represents exception mode.
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*/
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uint32_t m0_exception_mode:2;
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/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
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* Represents exception id information.
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*/
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uint32_t m0_exception_id:5;
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uint32_t reserved_23:9;
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};
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uint32_t val;
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} hp_apm_m0_exception_info0_reg_t;
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/** Group: M0 exception_info1 register */
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/** Type of m0_exception_info1 register
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* M0 exception_info1 register
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*/
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typedef union {
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struct {
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/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
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* Represents exception addr.
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*/
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uint32_t m0_exception_addr:32;
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};
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uint32_t val;
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} hp_apm_m0_exception_info1_reg_t;
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/** Group: M1 status register */
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/** Type of m1_status register
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* M1 status register
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*/
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typedef union {
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struct {
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/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
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* Represents exception status.\\
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* bit0: 1 represents authority_exception \\
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* bit1: 1 represents space_exception \\
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*/
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uint32_t m1_exception_status:2;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} hp_apm_m1_status_reg_t;
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/** Group: M1 status clear register */
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/** Type of m1_status_clr register
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* M1 status clear register
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*/
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typedef union {
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struct {
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/** m1_exception_status_clr : WT; bitpos: [0]; default: 0;
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* Configures to clear exception status.
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*/
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uint32_t m1_exception_status_clr:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} hp_apm_m1_status_clr_reg_t;
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/** Group: M1 exception_info0 register */
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/** Type of m1_exception_info0 register
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* M1 exception_info0 register
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*/
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typedef union {
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struct {
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/** m1_exception_region : RO; bitpos: [15:0]; default: 0;
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* Represents exception region.
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*/
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uint32_t m1_exception_region:16;
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/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
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* Represents exception mode.
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*/
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uint32_t m1_exception_mode:2;
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/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
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* Represents exception id information.
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*/
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uint32_t m1_exception_id:5;
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uint32_t reserved_23:9;
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};
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uint32_t val;
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} hp_apm_m1_exception_info0_reg_t;
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/** Group: M1 exception_info1 register */
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/** Type of m1_exception_info1 register
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* M1 exception_info1 register
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*/
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typedef union {
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struct {
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/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
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* Represents exception addr.
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*/
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uint32_t m1_exception_addr:32;
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};
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uint32_t val;
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} hp_apm_m1_exception_info1_reg_t;
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/** Group: M2 status register */
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/** Type of m2_status register
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* M2 status register
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*/
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typedef union {
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struct {
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/** m2_exception_status : RO; bitpos: [1:0]; default: 0;
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* Represents exception status.\\
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* bit0: 1 represents authority_exception \\
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* bit1: 1 represents space_exception \\
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*/
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uint32_t m2_exception_status:2;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} hp_apm_m2_status_reg_t;
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/** Group: M2 status clear register */
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/** Type of m2_status_clr register
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* M2 status clear register
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*/
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typedef union {
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struct {
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/** m2_exception_status_clr : WT; bitpos: [0]; default: 0;
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* Configures to clear exception status.
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*/
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uint32_t m2_exception_status_clr:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} hp_apm_m2_status_clr_reg_t;
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/** Group: M2 exception_info0 register */
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/** Type of m2_exception_info0 register
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* M2 exception_info0 register
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*/
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typedef union {
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struct {
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/** m2_exception_region : RO; bitpos: [15:0]; default: 0;
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* Represents exception region.
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*/
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uint32_t m2_exception_region:16;
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/** m2_exception_mode : RO; bitpos: [17:16]; default: 0;
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* Represents exception mode.
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*/
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uint32_t m2_exception_mode:2;
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/** m2_exception_id : RO; bitpos: [22:18]; default: 0;
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* Represents exception id information.
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*/
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uint32_t m2_exception_id:5;
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uint32_t reserved_23:9;
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};
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uint32_t val;
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} hp_apm_m2_exception_info0_reg_t;
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/** Group: M2 exception_info1 register */
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/** Type of m2_exception_info1 register
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* M2 exception_info1 register
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*/
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typedef union {
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struct {
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/** m2_exception_addr : RO; bitpos: [31:0]; default: 0;
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* Represents exception addr.
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*/
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uint32_t m2_exception_addr:32;
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};
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uint32_t val;
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} hp_apm_m2_exception_info1_reg_t;
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/** Group: M3 status register */
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/** Type of m3_status register
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* M3 status register
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*/
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typedef union {
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struct {
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/** m3_exception_status : RO; bitpos: [1:0]; default: 0;
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* Represents exception status.\\
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* bit0: 1 represents authority_exception \\
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* bit1: 1 represents space_exception \\
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*/
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uint32_t m3_exception_status:2;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} hp_apm_m3_status_reg_t;
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/** Group: M3 status clear register */
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/** Type of m3_status_clr register
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* M3 status clear register
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*/
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typedef union {
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struct {
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/** m3_exception_status_clr : WT; bitpos: [0]; default: 0;
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* Configures to clear exception status.
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*/
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uint32_t m3_exception_status_clr:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} hp_apm_m3_status_clr_reg_t;
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/** Group: M3 exception_info0 register */
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/** Type of m3_exception_info0 register
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* M3 exception_info0 register
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*/
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typedef union {
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struct {
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/** m3_exception_region : RO; bitpos: [15:0]; default: 0;
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* Represents exception region.
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*/
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uint32_t m3_exception_region:16;
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/** m3_exception_mode : RO; bitpos: [17:16]; default: 0;
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* Represents exception mode.
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*/
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uint32_t m3_exception_mode:2;
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/** m3_exception_id : RO; bitpos: [22:18]; default: 0;
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* Represents exception id information.
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*/
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uint32_t m3_exception_id:5;
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uint32_t reserved_23:9;
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};
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uint32_t val;
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} hp_apm_m3_exception_info0_reg_t;
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/** Group: M3 exception_info1 register */
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/** Type of m3_exception_info1 register
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* M3 exception_info1 register
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*/
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typedef union {
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struct {
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/** m3_exception_addr : RO; bitpos: [31:0]; default: 0;
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* Represents exception addr.
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*/
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uint32_t m3_exception_addr:32;
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};
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uint32_t val;
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} hp_apm_m3_exception_info1_reg_t;
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/** Group: APM interrupt enable register */
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/** Type of int_en register
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* APM interrupt enable register
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*/
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typedef union {
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struct {
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/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
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* Configures to enable APM M0 interrupt.\\
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* 0: disable \\
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* 1: enable \\
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*/
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uint32_t m0_apm_int_en:1;
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/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
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* Configures to enable APM M1 interrupt.\\
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* 0: disable \\
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* 1: enable \\
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*/
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uint32_t m1_apm_int_en:1;
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/** m2_apm_int_en : R/W; bitpos: [2]; default: 0;
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* Configures to enable APM M2 interrupt.\\
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* 0: disable \\
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* 1: enable \\
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*/
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uint32_t m2_apm_int_en:1;
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/** m3_apm_int_en : R/W; bitpos: [3]; default: 0;
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* Configures to enable APM M3 interrupt.\\
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* 0: disable \\
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* 1: enable \\
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*/
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uint32_t m3_apm_int_en:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} hp_apm_int_en_reg_t;
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/** Group: Clock gating register */
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/** Type of clock_gate register
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* Clock gating register
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*/
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typedef union {
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struct {
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/** clk_en : R/W; bitpos: [0]; default: 1;
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* Configures whether to keep the clock always on.\\
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* 0: enable automatic clock gating \\
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* 1: keep the clock always on \\
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*/
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uint32_t clk_en:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} hp_apm_clock_gate_reg_t;
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/** Group: Version control register */
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/** Type of date register
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* Version control register
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [27:0]; default: 36774400;
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* Version control register.
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*/
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uint32_t date:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} hp_apm_date_reg_t;
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typedef struct {
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volatile hp_apm_region_filter_en_reg_t region_filter_en;
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volatile hp_apm_regionn_addr_start_reg_t region0_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region0_addr_end;
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volatile hp_apm_regionn_attr_reg_t region0_attr;
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volatile hp_apm_regionn_addr_start_reg_t region1_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region1_addr_end;
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volatile hp_apm_regionn_attr_reg_t region1_attr;
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volatile hp_apm_regionn_addr_start_reg_t region2_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region2_addr_end;
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volatile hp_apm_regionn_attr_reg_t region2_attr;
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volatile hp_apm_regionn_addr_start_reg_t region3_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region3_addr_end;
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volatile hp_apm_regionn_attr_reg_t region3_attr;
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volatile hp_apm_regionn_addr_start_reg_t region4_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region4_addr_end;
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volatile hp_apm_regionn_attr_reg_t region4_attr;
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volatile hp_apm_regionn_addr_start_reg_t region5_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region5_addr_end;
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volatile hp_apm_regionn_attr_reg_t region5_attr;
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volatile hp_apm_regionn_addr_start_reg_t region6_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region6_addr_end;
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volatile hp_apm_regionn_attr_reg_t region6_attr;
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volatile hp_apm_regionn_addr_start_reg_t region7_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region7_addr_end;
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volatile hp_apm_regionn_attr_reg_t region7_attr;
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volatile hp_apm_regionn_addr_start_reg_t region8_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region8_addr_end;
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volatile hp_apm_regionn_attr_reg_t region8_attr;
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volatile hp_apm_regionn_addr_start_reg_t region9_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region9_addr_end;
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volatile hp_apm_regionn_attr_reg_t region9_attr;
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volatile hp_apm_regionn_addr_start_reg_t region10_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region10_addr_end;
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volatile hp_apm_regionn_attr_reg_t region10_attr;
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volatile hp_apm_regionn_addr_start_reg_t region11_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region11_addr_end;
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volatile hp_apm_regionn_attr_reg_t region11_attr;
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volatile hp_apm_regionn_addr_start_reg_t region12_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region12_addr_end;
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volatile hp_apm_regionn_attr_reg_t region12_attr;
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volatile hp_apm_regionn_addr_start_reg_t region13_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region13_addr_end;
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volatile hp_apm_regionn_attr_reg_t region13_attr;
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volatile hp_apm_regionn_addr_start_reg_t region14_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region14_addr_end;
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volatile hp_apm_regionn_attr_reg_t region14_attr;
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volatile hp_apm_regionn_addr_start_reg_t region15_addr_start;
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volatile hp_apm_regionn_addr_end_reg_t region15_addr_end;
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volatile hp_apm_regionn_attr_reg_t region15_attr;
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volatile hp_apm_func_ctrl_reg_t func_ctrl;
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volatile hp_apm_m0_status_reg_t m0_status;
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volatile hp_apm_m0_status_clr_reg_t m0_status_clr;
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volatile hp_apm_m0_exception_info0_reg_t m0_exception_info0;
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volatile hp_apm_m0_exception_info1_reg_t m0_exception_info1;
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volatile hp_apm_m1_status_reg_t m1_status;
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volatile hp_apm_m1_status_clr_reg_t m1_status_clr;
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volatile hp_apm_m1_exception_info0_reg_t m1_exception_info0;
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volatile hp_apm_m1_exception_info1_reg_t m1_exception_info1;
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volatile hp_apm_m2_status_reg_t m2_status;
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volatile hp_apm_m2_status_clr_reg_t m2_status_clr;
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volatile hp_apm_m2_exception_info0_reg_t m2_exception_info0;
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volatile hp_apm_m2_exception_info1_reg_t m2_exception_info1;
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volatile hp_apm_m3_status_reg_t m3_status;
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volatile hp_apm_m3_status_clr_reg_t m3_status_clr;
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volatile hp_apm_m3_exception_info0_reg_t m3_exception_info0;
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volatile hp_apm_m3_exception_info1_reg_t m3_exception_info1;
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volatile hp_apm_int_en_reg_t int_en;
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uint32_t reserved_10c[443];
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volatile hp_apm_clock_gate_reg_t clock_gate;
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volatile hp_apm_date_reg_t date;
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} hp_apm_dev_t;
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extern hp_apm_dev_t HP_APM;
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#ifndef __cplusplus
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_Static_assert(sizeof(hp_apm_dev_t) == 0x800, "Invalid size of hp_apm_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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