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https://github.com/espressif/esp-idf.git
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bc74cf808d
This commit adds a Kconfig option, CONFIG_ULP_RISCV_INTERRUPT_ENABLE, to enable interrupts on the ULP RISC-V core on the esp32s2 and esp32s3.
84 lines
3.1 KiB
Plaintext
84 lines
3.1 KiB
Plaintext
menu "Ultra Low Power (ULP) Co-processor"
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depends on (SOC_ULP_SUPPORTED || SOC_RISCV_COPROC_SUPPORTED || SOC_LP_CORE_SUPPORTED)
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config ULP_COPROC_ENABLED
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bool "Enable Ultra Low Power (ULP) Co-processor"
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default "n"
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help
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Enable this feature if you plan to use the ULP Co-processor.
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Once this option is enabled, further ULP co-processor configuration will appear in the menu.
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choice ULP_COPROC_TYPE
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prompt "ULP Co-processor type"
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depends on ULP_COPROC_ENABLED
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default ULP_COPROC_TYPE_RISCV if (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3)
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help
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Choose the ULP Coprocessor type: ULP FSM (Finite State Machine) or ULP RISC-V.
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config ULP_COPROC_TYPE_FSM
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bool "ULP FSM (Finite State Machine)"
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depends on SOC_ULP_FSM_SUPPORTED
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config ULP_COPROC_TYPE_RISCV
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bool "ULP RISC-V"
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depends on SOC_RISCV_COPROC_SUPPORTED
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config ULP_COPROC_TYPE_LP_CORE
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bool "LP core RISC-V"
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depends on SOC_LP_CORE_SUPPORTED
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endchoice
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config ULP_COPROC_RESERVE_MEM
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int
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prompt "RTC slow memory reserved for coprocessor"
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depends on ULP_COPROC_ENABLED
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default 512 if IDF_TARGET_ESP32
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default 4096 if !IDF_TARGET_ESP32
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range 32 8176 if !IDF_TARGET_ESP32C6
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range 32 16352 if IDF_TARGET_ESP32C6
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range 32 32768 if IDF_TARGET_ESP32P4
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help
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Bytes of memory to reserve for ULP Co-processor firmware & data.
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Data is reserved at the beginning of RTC slow memory.
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menu "ULP RISC-V Settings"
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depends on ULP_COPROC_TYPE_RISCV
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config ULP_RISCV_INTERRUPT_ENABLE
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bool
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prompt "Enable ULP RISC-V interrupts"
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default "n"
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help
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Turn on this setting to enabled interrupts on the ULP RISC-V core.
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config ULP_RISCV_UART_BAUDRATE
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int
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prompt "Baudrate used by the bitbanged ULP RISC-V UART driver"
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default 9600
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help
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The accuracy of the bitbanged UART driver is limited, it is not
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recommend to increase the value above 19200.
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config ULP_RISCV_I2C_RW_TIMEOUT
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int
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prompt "Set timeout for ULP RISC-V I2C transaction timeout in ticks."
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default 500
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range -1 4294967295
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help
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Set the ULP RISC-V I2C read/write timeout. Set this value to -1
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if the ULP RISC-V I2C read and write APIs should wait forever.
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Please note that the tick rate of the ULP co-processor would be
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different than the OS tick rate of the main core and therefore
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can have different timeout value depending on which core the API
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is invoked on.
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endmenu
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config ULP_SHARED_MEM
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depends on ULP_COPROC_TYPE_LP_CORE
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hex
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default 0x8
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help
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Size of the shared memory defined in ulp_lp_core_memory_shared.c.
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Size should be kept in-sync with the size of the struct defined there.
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endmenu # Ultra Low Power (ULP) Co-processor
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