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339fcbf14d
Unified Memory protection API for all PMS-aware chips - ESP32S3 port
52 lines
1.3 KiB
C
52 lines
1.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/sensitive_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef union {
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struct {
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uint32_t cat0 : 2;
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uint32_t cat1 : 2;
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uint32_t cat2 : 2;
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uint32_t cat3 : 2;
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uint32_t cat4 : 2;
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uint32_t cat5 : 2;
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uint32_t cat6 : 2;
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uint32_t splitaddr : 8;
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uint32_t reserved : 10;
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};
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uint32_t val;
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} constrain_reg_fields_t;
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#define I_D_SRAM_SEGMENT_SIZE 0x10000
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#define I_D_SPLIT_LINE_ALIGN 0x100
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#define I_D_SPLIT_LINE_SHIFT 0x8
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#define I_D_FAULT_ADDR_SHIFT 0x2
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//IRAM0
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4
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//DRAM0
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#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1
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#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2
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//RTC FAST
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#define SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W 0x1
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#define SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R 0x2
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#define SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F 0x4
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#ifdef __cplusplus
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}
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#endif
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