mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
ce351790a8
This commit adds a subset of the DWC OTG configuration values to the 'usb_dwc_ll.h' file. Only relevant configuration values have been added. Some DWC OTG releated constants have also been moved from 'usb_dwc_hal.h' to 'usb_dwc_ll.h' and renamed.
434 lines
20 KiB
C
434 lines
20 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stddef.h>
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#include <stdint.h>
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#include <string.h>
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#include "sdkconfig.h"
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#include "soc/chip_revision.h"
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#include "hal/efuse_hal.h"
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#include "hal/usb_dwc_hal.h"
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#include "hal/usb_dwc_ll.h"
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#include "hal/assert.h"
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// ------------------------------------------------ Macros and Types ---------------------------------------------------
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// ---------------------- Constants ------------------------
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#define BENDPOINTADDRESS_NUM_MSK 0x0F //Endpoint number mask of the bEndpointAddress field of an endpoint descriptor
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#define BENDPOINTADDRESS_DIR_MSK 0x80 //Endpoint direction mask of the bEndpointAddress field of an endpoint descriptor
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#define CORE_REG_GSNPSID 0x4F54400A
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#define CORE_REG_GHWCFG1 0x00000000
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#define CORE_REG_GHWCFG2 0x224DD930
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#define CORE_REG_GHWCFG3 0x00C804B5
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#define CORE_REG_GHWCFG4 0xD3F0A030
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// -------------------- Configurable -----------------------
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/**
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* The following core interrupts will be enabled (listed LSB to MSB). Some of these
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* interrupts are enabled later than others.
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* - USB_DWC_LL_INTR_CORE_PRTINT
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* - USB_DWC_LL_INTR_CORE_HCHINT
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* - USB_DWC_LL_INTR_CORE_DISCONNINT
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* The following PORT interrupts cannot be masked, listed LSB to MSB
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* - USB_DWC_LL_INTR_HPRT_PRTCONNDET
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* - USB_DWC_LL_INTR_HPRT_PRTENCHNG
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* - USB_DWC_LL_INTR_HPRT_PRTOVRCURRCHNG
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*/
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#define CORE_INTRS_EN_MSK (USB_DWC_LL_INTR_CORE_DISCONNINT)
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//Interrupts that pertain to core events
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#define CORE_EVENTS_INTRS_MSK (USB_DWC_LL_INTR_CORE_DISCONNINT | \
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USB_DWC_LL_INTR_CORE_HCHINT)
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//Interrupt that pertain to host port events
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#define PORT_EVENTS_INTRS_MSK (USB_DWC_LL_INTR_HPRT_PRTCONNDET | \
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USB_DWC_LL_INTR_HPRT_PRTENCHNG | \
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USB_DWC_LL_INTR_HPRT_PRTOVRCURRCHNG)
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/**
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* The following channel interrupt bits are currently checked (in order LSB to MSB)
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* - USB_DWC_LL_INTR_CHAN_XFERCOMPL
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* - USB_DWC_LL_INTR_CHAN_CHHLTD
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* - USB_DWC_LL_INTR_CHAN_STALL
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* - USB_DWC_LL_INTR_CHAN_BBLEER
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* - USB_DWC_LL_INTR_CHAN_BNAINTR
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* - USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR
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*
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* Note the following points about channel interrupts:
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* - Not all bits are unmaskable under scatter/gather
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* - Those bits proxy their interrupt through the USB_DWC_LL_INTR_CHAN_CHHLTD bit
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* - USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR is always unmasked
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* - When USB_DWC_LL_INTR_CHAN_BNAINTR occurs, USB_DWC_LL_INTR_CHAN_CHHLTD will NOT.
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* - USB_DWC_LL_INTR_CHAN_AHBERR doesn't actually ever happen on our system (i.e., ESP32-S2, ESP32-S3):
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* - If the QTD list's starting address is an invalid address (e.g., NULL), the core will attempt to fetch that
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* address for a transfer descriptor and probably gets all zeroes. It will interpret the zero as a bad QTD and
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* return a USB_DWC_LL_INTR_CHAN_BNAINTR instead.
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* - If the QTD's buffer pointer is an invalid address, the core will attempt to read/write data to/from that
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* invalid buffer address with NO INDICATION OF ERROR. The transfer will be acknowledged and treated as
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* successful. Bad buffer pointers MUST BE CHECKED FROM HIGHER LAYERS INSTEAD.
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*/
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#define CHAN_INTRS_EN_MSK (USB_DWC_LL_INTR_CHAN_XFERCOMPL | \
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USB_DWC_LL_INTR_CHAN_CHHLTD | \
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USB_DWC_LL_INTR_CHAN_BNAINTR)
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#define CHAN_INTRS_ERROR_MSK (USB_DWC_LL_INTR_CHAN_STALL | \
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USB_DWC_LL_INTR_CHAN_BBLEER | \
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USB_DWC_LL_INTR_CHAN_BNAINTR | \
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USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR)
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// -------------------------------------------------- Core (Global) ----------------------------------------------------
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static void set_defaults(usb_dwc_hal_context_t *hal)
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{
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//GAHBCFG register
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usb_dwc_ll_gahbcfg_en_dma_mode(hal->dev);
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int hbstlen = 0; //Use AHB burst SINGLE by default
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#if CONFIG_IDF_TARGET_ESP32S2 && CONFIG_ESP32S2_REV_MIN_FULL < 100
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/*
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Hardware errata workaround for the ESP32-S2 ECO0 (see ESP32-S2 Errata Document section 4.0 for full details).
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ESP32-S2 ECO0 has a hardware errata where the AHB bus arbiter may generate incorrect arbitration signals leading to
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the DWC_OTG corrupting the DMA transfers of other peripherals (or vice versa) on the same bus. The peripherals that
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share the same bus with DWC_OTG include I2C and SPI (see ESP32-S2 Errata Document for more details). To workaround
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this, the DWC_OTG's AHB should use INCR mode to prevent change of arbitration during a burst operation, thus
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avoiding this errata.
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Note: Setting AHB burst to INCR increases the likeliness of DMA underruns on other peripherals sharing the same bus
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arbiter as the DWC_OTG (e.g., I2C and SPI) as change of arbitration during the burst operation is not permitted.
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Users should keep this limitation in mind when the DWC_OTG transfers large data payloads (e.g., 512 MPS transfers)
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while this workaround is enabled.
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*/
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if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 100)) {
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hbstlen = 1; //Set AHB burst to INCR to workaround hardware errata
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}
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#endif //CONFIG_IDF_TARGET_ESP32S2 && CONFIG_ESP32S2_REV_MIN_FULL < 100
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usb_dwc_ll_gahbcfg_set_hbstlen(hal->dev, hbstlen); //Set AHB burst mode
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//GUSBCFG register
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usb_dwc_ll_gusbcfg_dis_hnp_cap(hal->dev); //Disable HNP
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usb_dwc_ll_gusbcfg_dis_srp_cap(hal->dev); //Disable SRP
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//Enable interruts
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usb_dwc_ll_gintmsk_dis_intrs(hal->dev, 0xFFFFFFFF); //Mask all interrupts first
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usb_dwc_ll_gintmsk_en_intrs(hal->dev, CORE_INTRS_EN_MSK); //Unmask global interrupts
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usb_dwc_ll_gintsts_read_and_clear_intrs(hal->dev); //Clear interrupts
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usb_dwc_ll_gahbcfg_en_global_intr(hal->dev); //Enable interrupt signal
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//Enable host mode
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usb_dwc_ll_gusbcfg_force_host_mode(hal->dev);
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}
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void usb_dwc_hal_init(usb_dwc_hal_context_t *hal)
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{
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//Check if a peripheral is alive by reading the core ID registers
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usb_dwc_dev_t *dev = &USB_DWC;
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uint32_t core_id = usb_dwc_ll_gsnpsid_get_id(dev);
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HAL_ASSERT(core_id == CORE_REG_GSNPSID);
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(void) core_id; //Suppress unused variable warning if asserts are disabled
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//Initialize HAL context
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memset(hal, 0, sizeof(usb_dwc_hal_context_t));
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hal->dev = dev;
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set_defaults(hal);
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}
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void usb_dwc_hal_deinit(usb_dwc_hal_context_t *hal)
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{
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//Disable and clear global interrupt
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usb_dwc_ll_gintmsk_dis_intrs(hal->dev, 0xFFFFFFFF); //Disable all interrupts
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usb_dwc_ll_gintsts_read_and_clear_intrs(hal->dev); //Clear interrupts
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usb_dwc_ll_gahbcfg_dis_global_intr(hal->dev); //Disable interrupt signal
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hal->dev = NULL;
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}
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void usb_dwc_hal_core_soft_reset(usb_dwc_hal_context_t *hal)
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{
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usb_dwc_ll_grstctl_core_soft_reset(hal->dev);
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while (usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(hal->dev)) {
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; //Wait until core reset is done
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}
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while (!usb_dwc_ll_grstctl_is_ahb_idle(hal->dev)) {
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; //Wait until AHB Master bus is idle before doing any other operations
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}
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//Set the default bits
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set_defaults(hal);
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//Clear all the flags and channels
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hal->periodic_frame_list = NULL;
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hal->flags.val = 0;
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hal->channels.num_allocd = 0;
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hal->channels.chan_pend_intrs_msk = 0;
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memset(hal->channels.hdls, 0, sizeof(usb_dwc_hal_chan_t *) * USB_DWC_NUM_HOST_CHAN);
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}
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void usb_dwc_hal_set_fifo_size(usb_dwc_hal_context_t *hal, const usb_dwc_hal_fifo_config_t *fifo_config)
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{
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HAL_ASSERT((fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines + fifo_config->ptx_fifo_lines) <= USB_DWC_FIFO_TOTAL_USABLE_LINES);
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//Check that none of the channels are active
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for (int i = 0; i < USB_DWC_NUM_HOST_CHAN; i++) {
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if (hal->channels.hdls[i] != NULL) {
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HAL_ASSERT(!hal->channels.hdls[i]->flags.active);
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}
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}
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//Set the new FIFO lengths
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usb_dwc_ll_grxfsiz_set_fifo_size(hal->dev, fifo_config->rx_fifo_lines);
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usb_dwc_ll_gnptxfsiz_set_fifo_size(hal->dev, fifo_config->rx_fifo_lines, fifo_config->nptx_fifo_lines);
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usb_dwc_ll_hptxfsiz_set_ptx_fifo_size(hal->dev, fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines, fifo_config->ptx_fifo_lines);
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//Flush the FIFOs
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usb_dwc_ll_grstctl_flush_nptx_fifo(hal->dev);
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usb_dwc_ll_grstctl_flush_ptx_fifo(hal->dev);
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usb_dwc_ll_grstctl_flush_rx_fifo(hal->dev);
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hal->flags.fifo_sizes_set = 1;
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}
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// ---------------------------------------------------- Host Port ------------------------------------------------------
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static inline void debounce_lock_enable(usb_dwc_hal_context_t *hal)
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{
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//Disable the hprt (connection) and disconnection interrupts to prevent repeated triggerings
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usb_dwc_ll_gintmsk_dis_intrs(hal->dev, USB_DWC_LL_INTR_CORE_PRTINT | USB_DWC_LL_INTR_CORE_DISCONNINT);
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hal->flags.dbnc_lock_enabled = 1;
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}
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void usb_dwc_hal_port_enable(usb_dwc_hal_context_t *hal)
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{
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usb_priv_speed_t speed = usb_dwc_ll_hprt_get_speed(hal->dev);
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//Host Configuration
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usb_dwc_ll_hcfg_set_defaults(hal->dev, speed);
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//Configure HFIR
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usb_dwc_ll_hfir_set_defaults(hal->dev, speed);
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}
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// ----------------------------------------------------- Channel -------------------------------------------------------
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// ----------------- Channel Allocation --------------------
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bool usb_dwc_hal_chan_alloc(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj, void *chan_ctx)
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{
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HAL_ASSERT(hal->flags.fifo_sizes_set); //FIFO sizes should be set befor attempting to allocate a channel
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//Attempt to allocate channel
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if (hal->channels.num_allocd == USB_DWC_NUM_HOST_CHAN) {
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return false; //Out of free channels
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}
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int chan_idx = -1;
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for (int i = 0; i < USB_DWC_NUM_HOST_CHAN; i++) {
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if (hal->channels.hdls[i] == NULL) {
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hal->channels.hdls[i] = chan_obj;
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chan_idx = i;
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hal->channels.num_allocd++;
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break;
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}
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}
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HAL_ASSERT(chan_idx != -1);
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//Initialize channel object
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memset(chan_obj, 0, sizeof(usb_dwc_hal_chan_t));
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chan_obj->flags.chan_idx = chan_idx;
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chan_obj->regs = usb_dwc_ll_chan_get_regs(hal->dev, chan_idx);
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chan_obj->chan_ctx = chan_ctx;
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//Note: EP characteristics configured separately
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//Clean and unmask the channel's interrupt
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usb_dwc_ll_hcint_read_and_clear_intrs(chan_obj->regs); //Clear the interrupt bits for that channel
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usb_dwc_ll_haintmsk_en_chan_intr(hal->dev, 1 << chan_obj->flags.chan_idx);
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usb_dwc_ll_hcintmsk_set_intr_mask(chan_obj->regs, CHAN_INTRS_EN_MSK); //Unmask interrupts for this channel
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usb_dwc_ll_hctsiz_set_pid(chan_obj->regs, 0); //Set the initial PID to zero
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usb_dwc_ll_hctsiz_init(chan_obj->regs); //Set the non changing parts of the HCTSIZ registers (e.g., do_ping and sched info)
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return true;
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}
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void usb_dwc_hal_chan_free(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj)
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{
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if (chan_obj->type == USB_PRIV_XFER_TYPE_INTR || chan_obj->type == USB_PRIV_XFER_TYPE_ISOCHRONOUS) {
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//Unschedule this channel
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for (int i = 0; i < hal->frame_list_len; i++) {
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hal->periodic_frame_list[i] &= ~(1 << chan_obj->flags.chan_idx);
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}
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}
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//Can only free a channel when in the disabled state and descriptor list released
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HAL_ASSERT(!chan_obj->flags.active);
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//Disable channel's interrupt
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usb_dwc_ll_haintmsk_dis_chan_intr(hal->dev, 1 << chan_obj->flags.chan_idx);
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//Deallocate channel
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hal->channels.hdls[chan_obj->flags.chan_idx] = NULL;
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hal->channels.num_allocd--;
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HAL_ASSERT(hal->channels.num_allocd >= 0);
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}
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// ---------------- Channel Configuration ------------------
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void usb_dwc_hal_chan_set_ep_char(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj, usb_dwc_hal_ep_char_t *ep_char)
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{
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//Cannot change ep_char whilst channel is still active or in error
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HAL_ASSERT(!chan_obj->flags.active);
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//Set the endpoint characteristics of the pipe
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usb_dwc_ll_hcchar_init(chan_obj->regs,
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ep_char->dev_addr,
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ep_char->bEndpointAddress & BENDPOINTADDRESS_NUM_MSK,
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ep_char->mps,
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ep_char->type,
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ep_char->bEndpointAddress & BENDPOINTADDRESS_DIR_MSK,
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ep_char->ls_via_fs_hub);
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//Save channel type
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chan_obj->type = ep_char->type;
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//If this is a periodic endpoint/channel, set its schedule in the frame list
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if (ep_char->type == USB_PRIV_XFER_TYPE_ISOCHRONOUS || ep_char->type == USB_PRIV_XFER_TYPE_INTR) {
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HAL_ASSERT((int)ep_char->periodic.interval <= (int)hal->frame_list_len); //Interval cannot exceed the length of the frame list
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//Find the effective offset in the frame list (in case the phase_offset_frames > interval)
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int offset = ep_char->periodic.phase_offset_frames % ep_char->periodic.interval;
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//Schedule the channel in the frame list
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for (int i = offset; i < hal->frame_list_len; i+= ep_char->periodic.interval) {
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hal->periodic_frame_list[i] |= 1 << chan_obj->flags.chan_idx;
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}
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}
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}
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// ------------------- Channel Control ---------------------
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void usb_dwc_hal_chan_activate(usb_dwc_hal_chan_t *chan_obj, void *xfer_desc_list, int desc_list_len, int start_idx)
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{
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//Cannot activate a channel that has already been enabled or is pending error handling
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HAL_ASSERT(!chan_obj->flags.active);
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//Set start address of the QTD list and starting QTD index
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usb_dwc_ll_hcdma_set_qtd_list_addr(chan_obj->regs, xfer_desc_list, start_idx);
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usb_dwc_ll_hctsiz_set_qtd_list_len(chan_obj->regs, desc_list_len);
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usb_dwc_ll_hcchar_enable_chan(chan_obj->regs); //Start the channel
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chan_obj->flags.active = 1;
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}
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bool usb_dwc_hal_chan_request_halt(usb_dwc_hal_chan_t *chan_obj)
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{
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if (chan_obj->flags.active) {
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/*
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Request a halt so long as the channel's active flag is set.
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- If the underlying hardware channel is already halted but the channel is pending interrupt handling,
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disabling the channel will have no effect (i.e., no channel interrupt is generated).
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- If the underlying channel is currently active, disabling the channel will trigger a channel interrupt.
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Regardless, setting the "halt_requested" should cause "usb_dwc_hal_chan_decode_intr()" to report the
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USB_DWC_HAL_CHAN_EVENT_HALT_REQ event when channel interrupt is handled (pending or triggered).
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*/
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usb_dwc_ll_hcchar_disable_chan(chan_obj->regs);
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chan_obj->flags.halt_requested = 1;
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return false;
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} else {
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//Channel was never active to begin with, simply return true
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return true;
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}
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}
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// ------------------------------------------------- Event Handling ----------------------------------------------------
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usb_dwc_hal_port_event_t usb_dwc_hal_decode_intr(usb_dwc_hal_context_t *hal)
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{
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uint32_t intrs_core = usb_dwc_ll_gintsts_read_and_clear_intrs(hal->dev); //Read and clear core interrupts
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uint32_t intrs_port = 0;
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if (intrs_core & USB_DWC_LL_INTR_CORE_PRTINT) {
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//There are host port interrupts. Read and clear those as well.
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intrs_port = usb_dwc_ll_hprt_intr_read_and_clear(hal->dev);
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}
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//Note: Do not change order of checks. Regressing events (e.g. enable -> disabled, connected -> connected)
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//always take precedence. ENABLED < DISABLED < CONN < DISCONN < OVRCUR
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usb_dwc_hal_port_event_t event = USB_DWC_HAL_PORT_EVENT_NONE;
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//Check if this is a core or port event
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if ((intrs_core & CORE_EVENTS_INTRS_MSK) || (intrs_port & PORT_EVENTS_INTRS_MSK)) {
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//Do not change the order of the following checks. Some events/interrupts take precedence over others
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if (intrs_core & USB_DWC_LL_INTR_CORE_DISCONNINT) {
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event = USB_DWC_HAL_PORT_EVENT_DISCONN;
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debounce_lock_enable(hal);
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//Mask the port connection and disconnection interrupts to prevent repeated triggering
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} else if (intrs_port & USB_DWC_LL_INTR_HPRT_PRTOVRCURRCHNG) {
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//Check if this is an overcurrent or an overcurrent cleared
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if (usb_dwc_ll_hprt_get_port_overcur(hal->dev)) {
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event = USB_DWC_HAL_PORT_EVENT_OVRCUR;
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} else {
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event = USB_DWC_HAL_PORT_EVENT_OVRCUR_CLR;
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}
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} else if (intrs_port & USB_DWC_LL_INTR_HPRT_PRTENCHNG) {
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if (usb_dwc_ll_hprt_get_port_en(hal->dev)) { //Host port was enabled
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event = USB_DWC_HAL_PORT_EVENT_ENABLED;
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} else { //Host port has been disabled
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event = USB_DWC_HAL_PORT_EVENT_DISABLED;
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}
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} else if (intrs_port & USB_DWC_LL_INTR_HPRT_PRTCONNDET && !hal->flags.dbnc_lock_enabled) {
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event = USB_DWC_HAL_PORT_EVENT_CONN;
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debounce_lock_enable(hal);
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}
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}
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//Port events always take precedence over channel events
|
|
if (event == USB_DWC_HAL_PORT_EVENT_NONE && (intrs_core & USB_DWC_LL_INTR_CORE_HCHINT)) {
|
|
//One or more channels have pending interrupts. Store the mask of those channels
|
|
hal->channels.chan_pend_intrs_msk = usb_dwc_ll_haint_get_chan_intrs(hal->dev);
|
|
event = USB_DWC_HAL_PORT_EVENT_CHAN;
|
|
}
|
|
|
|
return event;
|
|
}
|
|
|
|
usb_dwc_hal_chan_t *usb_dwc_hal_get_chan_pending_intr(usb_dwc_hal_context_t *hal)
|
|
{
|
|
int chan_num = __builtin_ffs(hal->channels.chan_pend_intrs_msk);
|
|
if (chan_num) {
|
|
hal->channels.chan_pend_intrs_msk &= ~(1 << (chan_num - 1)); //Clear the pending bit for that channel
|
|
return hal->channels.hdls[chan_num - 1];
|
|
} else {
|
|
return NULL;
|
|
}
|
|
}
|
|
|
|
usb_dwc_hal_chan_event_t usb_dwc_hal_chan_decode_intr(usb_dwc_hal_chan_t *chan_obj)
|
|
{
|
|
uint32_t chan_intrs = usb_dwc_ll_hcint_read_and_clear_intrs(chan_obj->regs);
|
|
usb_dwc_hal_chan_event_t chan_event;
|
|
//Note: We don't assert on (chan_obj->flags.active) here as it could have been already cleared by usb_dwc_hal_chan_request_halt()
|
|
|
|
/*
|
|
Note: Do not change order of checks as some events take precedence over others.
|
|
Errors > Channel Halt Request > Transfer completed
|
|
*/
|
|
if (chan_intrs & CHAN_INTRS_ERROR_MSK) { //Note: Errors are uncommon, so we check against the entire interrupt mask to reduce frequency of entering this call path
|
|
HAL_ASSERT(chan_intrs & USB_DWC_LL_INTR_CHAN_CHHLTD); //An error should have halted the channel
|
|
//Store the error in hal context
|
|
usb_dwc_hal_chan_error_t error;
|
|
if (chan_intrs & USB_DWC_LL_INTR_CHAN_STALL) {
|
|
error = USB_DWC_HAL_CHAN_ERROR_STALL;
|
|
} else if (chan_intrs & USB_DWC_LL_INTR_CHAN_BBLEER) {
|
|
error = USB_DWC_HAL_CHAN_ERROR_PKT_BBL;
|
|
} else if (chan_intrs & USB_DWC_LL_INTR_CHAN_BNAINTR) {
|
|
error = USB_DWC_HAL_CHAN_ERROR_BNA;
|
|
} else { //USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR
|
|
error = USB_DWC_HAL_CHAN_ERROR_XCS_XACT;
|
|
}
|
|
//Update flags
|
|
chan_obj->error = error;
|
|
chan_obj->flags.active = 0;
|
|
//Save the error to be handled later
|
|
chan_event = USB_DWC_HAL_CHAN_EVENT_ERROR;
|
|
} else if (chan_intrs & USB_DWC_LL_INTR_CHAN_CHHLTD) {
|
|
if (chan_obj->flags.halt_requested) {
|
|
chan_obj->flags.halt_requested = 0;
|
|
chan_event = USB_DWC_HAL_CHAN_EVENT_HALT_REQ;
|
|
} else {
|
|
//Must have been halted due to QTD HOC
|
|
chan_event = USB_DWC_HAL_CHAN_EVENT_CPLT;
|
|
}
|
|
chan_obj->flags.active = 0;
|
|
} else if (chan_intrs & USB_DWC_LL_INTR_CHAN_XFERCOMPL) {
|
|
/*
|
|
A transfer complete interrupt WITHOUT the channel halting only occurs when receiving a short interrupt IN packet
|
|
and the underlying QTD does not have the HOC bit set. This signifies the last packet of the Interrupt transfer
|
|
as all interrupt packets must MPS sized except the last.
|
|
*/
|
|
//The channel isn't halted yet, so we need to halt it manually to stop the execution of the next QTD/packet
|
|
usb_dwc_ll_hcchar_disable_chan(chan_obj->regs);
|
|
/*
|
|
After setting the halt bit, this will generate another channel halted interrupt. We treat this interrupt as
|
|
a NONE event, then cycle back with the channel halted interrupt to handle the CPLT event.
|
|
*/
|
|
chan_event = USB_DWC_HAL_CHAN_EVENT_NONE;
|
|
} else {
|
|
abort(); //Should never reach this point
|
|
}
|
|
return chan_event;
|
|
}
|