Michael (XIAO Xufeng) 2b7681ec4f esp_flash: fix set qe bit and write command issues ... There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.		2019-11-21 12:26:14 +08:00
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esp_flash_internal.h	esp_flash: fix the coredump issue	2019-09-18 14:30:23 +08:00
esp_flash_spi_init.h	esp_flash: fix set qe bit and write command issues	2019-11-21 12:26:14 +08:00
esp_flash.h	esp_flash: fix set qe bit and write command issues	2019-11-21 12:26:14 +08:00
esp_partition.h	esp_partition_erase_range(): rename parameter "start_addr" to "offset"	2019-07-08 17:29:05 +10:00
esp_spi_flash.h	spi_flash: support working on differnt buses and frequency	2019-06-18 06:32:52 +00:00
memspi_host_driver.h	esp_flash: fix set qe bit and write command issues	2019-11-21 12:26:14 +08:00
spi_flash_chip_driver.h	esp_flash: fix set qe bit and write command issues	2019-11-21 12:26:14 +08:00
spi_flash_chip_generic.h	esp_flash: fix set qe bit and write command issues	2019-11-21 12:26:14 +08:00
spi_flash_chip_issi.h	spi_flash: support working on differnt buses and frequency	2019-06-18 06:32:52 +00:00