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3336b057d6
Upstream xtensa exception handling will save PS, PC, and a0 registers together when saving a minimal context. This commit ppdates the xtensa exception handling to match upstream behavior.
41 lines
1.3 KiB
ArmAsm
41 lines
1.3 KiB
ArmAsm
#include "freertos/xtensa_rtos.h"
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// ------------------------------------------------
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.section .iram1,"ax"
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.global gdbstub_handle_uart_int
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.global _xt_gdbstub_int
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.align 4
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_xt_gdbstub_int:
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/* Allocate exception frame and save minimal context. */
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mov a0, sp
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addi sp, sp, -XT_STK_FRMSZ
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s32i a0, sp, XT_STK_A1
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#if XCHAL_HAVE_WINDOWED
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s32e a0, sp, -12 /* for debug backtrace */
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#endif
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rsr a0, PS /* save interruptee's PS */
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s32i a0, sp, XT_STK_PS
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rsr a0, EPC_1 /* save interruptee's PC */
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s32i a0, sp, XT_STK_PC
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rsr a0, EXCSAVE_1 /* save interruptee's a0 */
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s32i a0, sp, XT_STK_A0
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#if XCHAL_HAVE_WINDOWED
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s32e a0, sp, -16 /* for debug backtrace */
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#endif
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s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */
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s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */
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/* Save exc cause and vaddr into exception frame */
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rsr a0, EXCCAUSE
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s32i a0, sp, XT_STK_EXCCAUSE
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rsr a0, EXCVADDR
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s32i a0, sp, XT_STK_EXCVADDR
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mov a6,sp
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movi a3, gdbstub_handle_uart_int
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callx0 a3
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ret
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