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esp-idf/components/ulp/ulp_riscv
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Marius Vikhammer a2d2f30816 Merge branch 'contrib/github_pr_14010_v5.3' into 'release/v5.3' 
fix(ulp): Write pin's output mode to the correct register (GitHub PR) (v5.3)

See merge request espressif/esp-idf!31595
2024-07-25 16:24:35 +08:00
..
include fix(ulp): enable astyle linter and format ULP component 2024-01-22 11:43:38 +08:00
shared/include ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP. 2022-08-05 18:16:31 +08:00
ulp_core fix(ulp-risc-v): Set RTC GPIO output mode in the correct register for ULP RISC-V 2024-06-19 08:59:57 +02:00
ulp_riscv_i2c.c Merge branch 'fix/ulp_riscv_i2c_multi_byte_v5.3' into 'release/v5.3' 2024-07-25 16:24:18 +08:00
ulp_riscv_lock.c ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP. 2022-08-05 18:16:31 +08:00
ulp_riscv.c fix(ulp): enable astyle linter and format ULP component 2024-01-22 11:43:38 +08:00