mirror of
https://github.com/espressif/esp-idf.git
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cb6e2133f0
The commit fixes the case: If variables in RTC RAM have been moved around by the linker, they will be filled with garbage data. Any reset other than OTA would work fine because the variables would still be initialized from the initial bootup. So now system time will be valid even after OTA. Closes https://github.com/espressif/esp-idf/issues/9448
112 lines
5.5 KiB
C
112 lines
5.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include "esp_attr.h"
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "heap_memory_layout.h"
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#include "esp_heap_caps.h"
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/**
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* @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
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* Each type of memory map consists of one or more regions in the address space.
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* Each type contains an array of prioritized capabilities.
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* Types with later entries are only taken if earlier ones can't fulfill the memory request.
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*
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* - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory.
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* - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
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* - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
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* - Most other malloc caps only fit in one region anyway.
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*
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*/
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/* Index of memory in `soc_memory_types[]` */
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enum {
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SOC_MEMORY_TYPE_DRAM = 0,
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SOC_MEMORY_TYPE_STACK_DRAM = 1,
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SOC_MEMORY_TYPE_DIRAM = 2,
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SOC_MEMORY_TYPE_STACK_DIRAM = 3,
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SOC_MEMORY_TYPE_RTCRAM = 4,
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SOC_MEMORY_TYPE_NUM,
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};
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const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
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// Type 0: DRAM
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[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
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// Type 1: DRAM used for startup stacks
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[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
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// Type 2: DRAM which has an alias on the I-port
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[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
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// Type 3: DIRAM used for startup stacks
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[SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true},
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// Type 4: RTCRAM
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[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
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};
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#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM
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#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM
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#else
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#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
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#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM
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#endif
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const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
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/**
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* @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
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*
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* @note Because of requirements in the coalescing code which merges adjacent regions,
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* this list should always be sorted from low to high by start address.
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*
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*/
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/**
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* Register the shared buffer area of the last memory block into the heap during heap initialization
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*/
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#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
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const soc_memory_region_t soc_memory_regions[] = {
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{ 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory
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{ 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory
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{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory
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{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
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#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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{ 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory
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#endif
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};
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const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
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extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
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extern int _rtc_reserved_start, _rtc_reserved_end;
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/**
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* Reserved memory regions.
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* These are removed from the soc_memory_regions array when heaps are created.
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*
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*/
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// Static data region. DRAM used by data+bss and possibly rodata
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
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// Target has a big D/IRAM region, the part used by code is reserved
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// The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address
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#define I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code);
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#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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/* We use _rtc_force_slow_end not _rtc_noinit_end here, as rtc "fast" memory ends up in RTC SLOW
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region on C3, no differentiation. And _rtc_force_slow_end is the end of all the static RTC sections.
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*/
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SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
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#endif
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data);
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