mirror of
https://github.com/espressif/esp-idf.git
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61eb7baa6b
This commit updates the esp_cpu.h API. The new API presents a new
abstraction of the CPU where CPU presents the following interfaces:
- CPU Control (to stall/unstall/reset the CPU)
- CPU Registers (to read registers commonly used in SW such as SP, PC)
- CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts)
- Memory Port (to configure the CPU's memory bus for memory protection)
- Debugging (to configure/control the CPU's debugging port)
Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc
builds for esp_cpu.h
119 lines
2.7 KiB
C
119 lines
2.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stddef.h>
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#include <assert.h>
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#include "soc/soc.h"
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#include "riscv/interrupt.h"
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#include "soc/interrupt_reg.h"
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#include "riscv/csr.h"
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#include "esp_attr.h"
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#define RV_INT_COUNT 32
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static inline void assert_valid_rv_int_num(int rv_int_num)
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{
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assert(rv_int_num != 0 && rv_int_num < RV_INT_COUNT && "Invalid CPU interrupt number");
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}
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/*************************** Software interrupt dispatcher ***************************/
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typedef struct {
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intr_handler_t handler;
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void *arg;
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} intr_handler_item_t;
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static intr_handler_item_t s_intr_handlers[32];
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void intr_handler_set(int int_no, intr_handler_t fn, void *arg)
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{
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assert_valid_rv_int_num(int_no);
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s_intr_handlers[int_no] = (intr_handler_item_t) {
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.handler = fn,
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.arg = arg
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};
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}
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intr_handler_t intr_handler_get(int rv_int_num)
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{
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return s_intr_handlers[rv_int_num].handler;
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}
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void *intr_handler_get_arg(int rv_int_num)
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{
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return s_intr_handlers[rv_int_num].arg;
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}
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/* called from vectors.S */
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void _global_interrupt_handler(intptr_t sp, int mcause)
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{
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intr_handler_item_t it = s_intr_handlers[mcause];
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if (it.handler) {
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(*it.handler)(it.arg);
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}
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}
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/*************************** RISC-V interrupt enable/disable ***************************/
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void intr_matrix_route(int intr_src, int intr_num)
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{
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assert(intr_num != 0);
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REG_WRITE(DR_REG_INTERRUPT_BASE + 4 * intr_src, intr_num);
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}
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void riscv_global_interrupts_enable(void)
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{
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RV_SET_CSR(mstatus, MSTATUS_MIE);
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}
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void riscv_global_interrupts_disable(void)
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{
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RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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}
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uint32_t esprv_intc_get_interrupt_unmask(void)
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{
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return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
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}
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/*************************** ESP-RV Interrupt Controller ***************************/
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enum intr_type esprv_intc_int_get_type(int intr_num)
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{
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uint32_t intr_type_reg = REG_READ(INTERRUPT_CORE0_CPU_INT_TYPE_REG);
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return (intr_type_reg & (1 << intr_num)) ? INTR_TYPE_EDGE : INTR_TYPE_LEVEL;
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}
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int esprv_intc_int_get_priority(int rv_int_num)
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{
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uint32_t intr_priority_reg = REG_READ(INTC_INT_PRIO_REG(rv_int_num));
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return intr_priority_reg;
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}
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/*************************** Exception names. Used in .gdbinit file. ***************************/
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const char *riscv_excp_names[16] __attribute__((used)) = {
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"misaligned_fetch",
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"fault_fetch",
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"illegal_instruction",
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"breakpoint",
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"misaligned_load",
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"fault_load",
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"misaligned_store",
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"fault_store",
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"user_ecall",
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"supervisor_ecall",
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"hypervisor_ecall",
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"machine_ecall",
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"exec_page_fault",
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"load_page_fault",
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"reserved",
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"store_page_fault"
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};
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