Sachin Parekh 301dacfb33 Exception handlers for LoadStoreError and LoadStoreAlignmentError ... Configurable option to use IRAM as byte accessible memory (in single core mode) using load-store (non-word aligned and non-word size IRAM access specific) exception handlers. This allows to use IRAM for use-cases where certain performance penalty (upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration option has been provided to redirect mbedTLS specific in-out content length buffers to IRAM (in single core mode), allows to save 20KB per TLS connection.		2020-02-26 20:21:59 +08:00
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esp32	mbedtls: fix hw accelerated big-num mul if operand and result overlap	2020-01-09 18:11:18 +00:00
esp32s2	global: rename esp32s2beta to esp32s2	2020-01-22 12:14:38 +08:00
include	global: rename esp32s2beta to esp32s2	2020-01-22 12:14:38 +08:00
esp_hardware.c	mbedtls: import mbedtls project w/o modification	2018-11-27 13:59:26 +08:00
esp_mem.c	Exception handlers for LoadStoreError and LoadStoreAlignmentError	2020-02-26 20:21:59 +08:00
esp_sha1.c	global: rename esp32s2beta to esp32s2	2020-01-22 12:14:38 +08:00
esp_sha256.c	global: rename esp32s2beta to esp32s2	2020-01-22 12:14:38 +08:00
esp_sha512.c	global: rename esp32s2beta to esp32s2	2020-01-22 12:14:38 +08:00
esp_sha.c	global: rename esp32s2beta to esp32s2	2020-01-22 12:14:38 +08:00
esp_timing.c	Add DTLS support to libcoap using MbedTLS	2019-08-06 10:37:40 +05:30
mbedtls_debug.c	mbedtls: import mbedtls project w/o modification	2018-11-27 13:59:26 +08:00
net_sockets.c	Remove check for would_block in mbedtls	2019-10-17 16:36:18 +05:30