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https://github.com/espressif/esp-idf.git
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96b152a01f
This commit fixes an issue where in the ULP RISC-V I2C example causes a spurious wakeup of the main CPU because of a Trap signal when the ULP core does not meet the wakeup threshold values. This was due to the fact that the RTC_CNTL_COCPU_DONE signal was being set before the RTC_CNTL_COCPU_SHUT_RESET_EN signal which was causing the the ULP RISC-V core to not reset properly on each cycle. Closes https://github.com/espressif/esp-idf/issues/10301
48 lines
1.6 KiB
C
48 lines
1.6 KiB
C
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "ulp_riscv/ulp_riscv.h"
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#include "ulp_riscv/ulp_riscv_utils.h"
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void ulp_riscv_rescue_from_monitor(void)
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{
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/* Rescue RISCV from monitor state. */
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CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN);
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}
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void ulp_riscv_wakeup_main_processor(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SW_CPU_INT);
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}
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void ulp_riscv_shutdown(void)
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{
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/* Setting the delay time after RISCV recv `DONE` signal, Ensure that action `RESET` can be executed in time. */
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REG_SET_FIELD(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_2_CLK_DIS, 0x3F);
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/* Suspends the ulp operation and reset the ULP core. Must be the final operation before going to halt. */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN);
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while(1);
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}
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void ulp_riscv_delay_cycles(uint32_t cycles)
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{
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uint32_t start = ULP_RISCV_GET_CCOUNT();
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while ((ULP_RISCV_GET_CCOUNT() - start) < cycles) {
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/* Wait */
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}
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}
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