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https://github.com/espressif/esp-idf.git
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9f9da9ec96
1. add hal and low-level layer for timer group 2. add callback functions to handle interrupt 3. add timer deinit function 4. add timer spinlock take function
114 lines
3.9 KiB
C
114 lines
3.9 KiB
C
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "sdkconfig.h"
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include <esp_types.h>
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#include "esp_err.h"
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#include "esp_intr_alloc.h"
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#include "esp_attr.h"
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#include "esp_freertos_hooks.h"
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#include "soc/timer_periph.h"
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#include "driver/timer.h"
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#include "driver/periph_ctrl.h"
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#include "esp_int_wdt.h"
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#include "hal/timer_ll.h"
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#if CONFIG_ESP_INT_WDT
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#define TG1_WDT_TICK_US 500
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#define WDT_INT_NUM 24
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//Take care: the tick hook can also be called before esp_int_wdt_init() is called.
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#if CONFIG_ESP_INT_WDT_CHECK_CPU1
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//Not static; the ISR assembly checks this.
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bool int_wdt_app_cpu_ticked=false;
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static void IRAM_ATTR tick_hook(void) {
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if (xPortGetCoreID()!=0) {
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int_wdt_app_cpu_ticked=true;
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} else {
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//Only feed wdt if app cpu also ticked.
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if (int_wdt_app_cpu_ticked) {
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timer_ll_wdt_set_protect(&TIMERG1, false);
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//Set timeout before interrupt
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timer_ll_wdt_set_timeout(&TIMERG1, 0,
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CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/TG1_WDT_TICK_US);
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//Set timeout before reset
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timer_ll_wdt_set_timeout(&TIMERG1, 1,
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2*CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/TG1_WDT_TICK_US);
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timer_ll_wdt_feed(&TIMERG1);
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timer_ll_wdt_set_protect(&TIMERG1, true);
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int_wdt_app_cpu_ticked=false;
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}
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}
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}
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#else
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static void IRAM_ATTR tick_hook(void) {
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if (xPortGetCoreID()!=0) return;
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timer_ll_wdt_set_protect(&TIMERG1, false);
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//Set timeout before interrupt
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timer_ll_wdt_set_timeout(&TIMERG1, 0, CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/TG1_WDT_TICK_US);
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//Set timeout before reset
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timer_ll_wdt_set_timeout(&TIMERG1, 1, 2*CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/TG1_WDT_TICK_US);
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timer_ll_wdt_feed(&TIMERG1);
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timer_ll_wdt_set_protect(&TIMERG1, true);
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}
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#endif
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void esp_int_wdt_init(void) {
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periph_module_enable(PERIPH_TIMG1_MODULE);
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//The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets
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//it to their actual value.
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timer_ll_wdt_set_protect(&TIMERG1, false);
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timer_ll_wdt_init(&TIMERG1);
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timer_ll_wdt_set_tick(&TIMERG1, TG1_WDT_TICK_US); //Prescaler: wdt counts in ticks of TG1_WDT_TICK_US
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//1st stage timeout: interrupt
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timer_ll_wdt_set_timeout_behavior(&TIMERG1, 0, TIMER_WDT_INT);
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timer_ll_wdt_set_timeout(&TIMERG1, 0, 5*1000*1000/TG1_WDT_TICK_US);
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//2nd stage timeout: reset system
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timer_ll_wdt_set_timeout_behavior(&TIMERG1, 1, TIMER_WDT_RESET_SYSTEM);
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timer_ll_wdt_set_timeout(&TIMERG1, 1, 5*1000*1000/TG1_WDT_TICK_US);
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timer_ll_wdt_set_enable(&TIMERG1, true);
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timer_ll_wdt_feed(&TIMERG1);
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timer_ll_wdt_set_protect(&TIMERG1, true);
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timer_ll_wdt_clear_intr_status(&TIMERG1);
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timer_ll_wdt_enable_intr(&TIMERG1);
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}
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void esp_int_wdt_cpu_init(void)
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{
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esp_register_freertos_tick_hook_for_cpu(tick_hook, xPortGetCoreID());
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ESP_INTR_DISABLE(WDT_INT_NUM);
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intr_matrix_set(xPortGetCoreID(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
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//We do not register a handler for the interrupt because it is interrupt level 4 which
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//is not servicable from C. Instead, xtensa_vectors.S has a call to the panic handler for
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//this interrupt.
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ESP_INTR_ENABLE(WDT_INT_NUM);
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}
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#endif
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