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https://github.com/espressif/esp-idf.git
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2c2a62e323
- Support SOC ROOT clock source switch - Support CPU frequency change - Support RTC SLOW clock source switch - Support RTC SLOW clock + RC FAST calibration Remove FPGA build for esp32h2
195 lines
6.5 KiB
C
195 lines
6.5 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_rom_sys.h"
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#include "esp_attr.h"
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#include "soc/i2c_ana_mst_reg.h"
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#include "modem/modem_lpcon_reg.h"
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/**
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* BB - 0x67 - BIT0
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* TXRF - 0x6B - BIT1
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* SDM - 0x63 - BIT2
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* PLL - 0x62 - BIT3
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* BIAS - 0x6A - BIT4
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* BBPLL - 0x66 - BIT5
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* ULP - 0x61 - BIT6
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* SAR - 0x69 - BIT7
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* PMU - 0x6d - BIT8
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*/
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#define REGI2C_ULP_CAL_DEVICE_EN (BIT(6) << 4)
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#define REGI2C_SAR_I2C_DEVICE_EN (BIT(7) << 4)
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#define REGI2C_BBPLL_DEVICE_EN (BIT(5) << 4)
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#define REGI2C_BIAS_DEVICE_EN (BIT(4) << 4)
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#define REGI2C_PMU_DEVICE_EN (BIT(8) << 4)
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#define REGI2C_RTC_BUSY (BIT(25))
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#define REGI2C_RTC_BUSY_M (BIT(25))
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#define REGI2C_RTC_BUSY_V 0x1
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#define REGI2C_RTC_BUSY_S 25
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#define REGI2C_RTC_WR_CNTL (BIT(24))
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#define REGI2C_RTC_WR_CNTL_M (BIT(24))
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#define REGI2C_RTC_WR_CNTL_V 0x1
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#define REGI2C_RTC_WR_CNTL_S 24
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#define REGI2C_RTC_DATA 0x000000FF
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#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
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#define REGI2C_RTC_DATA_V 0xFF
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#define REGI2C_RTC_DATA_S 16
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#define REGI2C_RTC_ADDR 0x000000FF
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#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
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#define REGI2C_RTC_ADDR_V 0xFF
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#define REGI2C_RTC_ADDR_S 8
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#define REGI2C_RTC_SLAVE_ID 0x000000FF
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#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
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#define REGI2C_RTC_SLAVE_ID_V 0xFF
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#define REGI2C_RTC_SLAVE_ID_S 0
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/* SLAVE */
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#define REGI2C_BBPLL (0x66)
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#define REGI2C_BBPLL_HOSTID 0
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#define REGI2C_BIAS (0x6a)
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#define REGI2C_BIAS_HOSTID 0
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#define REGI2C_PMU (0x6d)
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#define REGI2C_PMU_HOSTID 0
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#define REGI2C_ULP_CAL (0x61)
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#define REGI2C_ULP_CAL_HOSTID 0
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#define REGI2C_SAR_I2C (0x69)
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#define REGI2C_SAR_I2C_HOSTID 0
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/* SLAVE END */
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static IRAM_ATTR void regi2c_enable_block(uint8_t block)
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{
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REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
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REG_SET_BIT(I2C_MST_DATE_REG, I2C_MST_CLK_EN);
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REG_SET_FIELD(I2C_MST_ANA_CONF2_REG, I2C_MST_ANA_CONF2, 0);
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/* Before config I2C register, enable corresponding slave. */
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switch (block) {
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case REGI2C_BBPLL :
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REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BBPLL_DEVICE_EN);
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break;
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case REGI2C_BIAS :
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REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BIAS_DEVICE_EN);
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break;
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case REGI2C_PMU :
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REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_PMU_DEVICE_EN);
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break;
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case REGI2C_ULP_CAL:
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REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_DEVICE_EN);
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break;
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case REGI2C_SAR_I2C:
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REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_DEVICE_EN);
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break;
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default:
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return;
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}
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}
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static IRAM_ATTR void regi2c_disable_block(uint8_t block)
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{
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switch (block) {
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case REGI2C_BBPLL :
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REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BBPLL_DEVICE_EN);
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break;
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case REGI2C_BIAS :
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REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BIAS_DEVICE_EN);
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break;
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case REGI2C_PMU:
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REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_PMU_DEVICE_EN);
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break;
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case REGI2C_ULP_CAL:
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REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_DEVICE_EN);
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break;
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case REGI2C_SAR_I2C:
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REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_DEVICE_EN);
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break;
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default:
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return;
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}
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}
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uint8_t IRAM_ATTR esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add)
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{
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regi2c_enable_block(block);
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(void)host_id;
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uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
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| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
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REG_WRITE(I2C_MST_I2C0_CTRL_REG, temp);
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while (REG_GET_BIT(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY));
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uint8_t ret = REG_GET_FIELD(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_DATA);
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regi2c_disable_block(block);
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return ret;
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}
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uint8_t IRAM_ATTR esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
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{
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assert(msb - lsb < 8);
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regi2c_enable_block(block);
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(void)host_id;
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uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
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| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
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REG_WRITE(I2C_MST_I2C0_CTRL_REG, temp);
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while (REG_GET_BIT(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY));
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uint32_t data = REG_GET_FIELD(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_DATA);
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uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
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regi2c_disable_block(block);
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return ret;
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}
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void IRAM_ATTR esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
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{
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(void)host_id;
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regi2c_enable_block(block);
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uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
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| ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
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| ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register;
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| (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
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REG_WRITE(I2C_MST_I2C0_CTRL_REG, temp);
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while (REG_GET_BIT(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY));
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regi2c_disable_block(block);
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}
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void IRAM_ATTR esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
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{
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(void)host_id;
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assert(msb - lsb < 8);
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regi2c_enable_block(block);
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/*Read the i2c bus register*/
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uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
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| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
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REG_WRITE(I2C_MST_I2C0_CTRL_REG, temp);
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while (REG_GET_BIT(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY));
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temp = REG_GET_FIELD(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_DATA);
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/*Write the i2c bus register*/
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temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)));
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temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp;
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temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
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| ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
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| ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S)
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| ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
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REG_WRITE(I2C_MST_I2C0_CTRL_REG, temp);
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while (REG_GET_BIT(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY));
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regi2c_disable_block(block);
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}
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