mirror of
https://github.com/espressif/esp-idf.git
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128 lines
3.9 KiB
C
128 lines
3.9 KiB
C
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdio.h>
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#include "esp_private/panic_internal.h"
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#include "riscv/rvruntime-frames.h"
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extern void esp_panic_handler(panic_info_t *);
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void panic_print_registers(const void *f, int core)
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{
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uint32_t *regs = (uint32_t *)f;
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// only print ABI name
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const char *desc[] = {
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"MEPC ", "RA ", "SP ", "GP ", "TP ", "T0 ", "T1 ", "T2 ",
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"S0/FP ", "S1 ", "A0 ", "A1 ", "A2 ", "A3 ", "A4 ", "A5 ",
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"A6 ", "A7 ", "S2 ", "S3 ", "S4 ", "S5 ", "S6 ", "S7 ",
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"S8 ", "S9 ", "S10 ", "S11 ", "T3 ", "T4 ", "T5 ", "T6 ",
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"MSTATUS ", "MTVEC ", "MCAUSE ", "MTVAL ", "MHARTID "
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};
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panic_print_str("Core ");
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panic_print_dec(((RvExcFrame *)f)->mhartid);
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panic_print_str(" register dump:");
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for (int x = 0; x < sizeof(desc) / sizeof(desc[0]); x += 4) {
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panic_print_str("\r\n");
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for (int y = 0; y < 4 && x + y < sizeof(desc) / sizeof(desc[0]); y++) {
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if (desc[x + y][0] != 0) {
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panic_print_str(desc[x + y]);
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panic_print_str(": 0x");
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panic_print_hex(regs[x + y]);
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panic_print_str(" ");
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}
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}
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}
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}
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void panic_soc_fill_info(void *f, panic_info_t *info)
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{
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// TODO ESP32-C3 IDF-2386 / support soc panic
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return;
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}
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void panic_arch_fill_info(void *frame, panic_info_t *info)
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{
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RvExcFrame *regs = (RvExcFrame *) frame;
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info->core = 0;
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info->exception = PANIC_EXCEPTION_FAULT;
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//Please keep in sync with PANIC_RSN_* defines
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static const char *reason[] = {
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"Instruction address misaligned",
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"Instruction access fault",
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"Illegal instruction",
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"Breakpoint",
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"Load address misaligned",
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"Load access fault",
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"Store address misaligned",
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"Store access fault",
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"Environment call from U-mode",
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"Environment call from S-mode",
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NULL,
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"Environment call from M-mode",
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"Instruction page fault",
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"Load page fault",
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NULL,
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"Store page fault",
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};
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if (regs->mcause < (sizeof(reason) / sizeof(reason[0]))) {
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if (reason[regs->mcause] != NULL) {
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info->reason = (reason[regs->mcause]);
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}
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}
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info->description = "Exception was unhandled.";
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info->addr = (void *) regs->mepc;
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info->frame = ®s;
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}
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void panic_print_backtrace(const void *frame, int core)
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{
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// Basic backtrace
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panic_print_str("\r\nStack memory:\n");
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uint32_t sp = (uint32_t)((RvExcFrame *)frame)->sp;
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const int per_line = 8;
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for (int x = 0; x < 1024; x += per_line * sizeof(uint32_t)) {
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uint32_t *spp = (uint32_t *)(sp + x);
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panic_print_hex(sp + x);
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panic_print_str(": ");
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for (int y = 0; y < per_line; y++) {
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panic_print_str("0x");
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panic_print_hex(spp[y]);
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panic_print_char(y == per_line - 1 ? '\n' : ' ');
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}
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}
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}
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uint32_t panic_get_address(const void *f)
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{
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return ((RvExcFrame *)f)->mepc;
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}
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uint32_t panic_get_cause(const void *f)
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{
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return ((RvExcFrame *)f)->mcause;
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}
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void panic_set_address(void *f, uint32_t addr)
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{
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((RvExcFrame *)f)->mepc = addr;
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}
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