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44bd6f72bc
Introduced in9c23b8e5and4f87a62f. To get higher speed, menuconfig options are added to put ISR and other functions into the IRAM. The interrupt flag ESP_INTR_FLAG_IRAM is also mistakenly set when the ISR is put into the IRAM. However callbacks, which are wrote by the user, are called in the master and slave ISR. The user may not be aware of that these callbacks are not disabled during flash operations. Any cache miss during flash operation will cause panic. Essentially IRAM functions and intrrupt flag ESP_INTR_FLAG_IRAM are different, the latter means not disabling the ISR during flash operations. New bus_config flag intr_flags is offered to help set the interrupt attribute, including priority level, SHARED, IRAM (not disabled during flash operations). It introduced a small BREAK to IDFv3.1 (but the same as IDFv3.0) that the user has to manually set IRAM flag now (therefore he's aware of the IRAM thing) to void the ISR being disabled during flash operations.
74 lines
2.8 KiB
Plaintext
74 lines
2.8 KiB
Plaintext
menu "Driver configurations"
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menu "ADC configuration"
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config ADC_FORCE_XPD_FSM
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bool "Use the FSM to control ADC power"
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default n
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help
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ADC power can be controlled by the FSM instead of software. This allows the ADC to
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be shut off when it is not working leading to lower power consumption. However
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using the FSM control ADC power will increase the noise of ADC.
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config ADC2_DISABLE_DAC
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bool "Disable DAC when ADC2 is used on GPIO 25 and 26"
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default y
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help
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If this is set, the ADC2 driver will disables the output of the DAC corresponding to the specified channel. This is the default value.
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For testing, disable this option so that we can measure the output of DAC by internal ADC.
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endmenu # ADC Configuration
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menu "SPI configuration"
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config SPI_MASTER_IN_IRAM
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bool "Place transmitting functions of SPI master into IRAM"
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default n
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select SPI_MASTER_ISR_IN_IRAM
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help
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Normally only the ISR of SPI master is placed in the IRAM, so that it
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can work without the flash when interrupt is triggered.
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For other functions, there's some possibility that the flash cache
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miss when running inside and out of SPI functions, which may increase
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the interval of SPI transactions.
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Enable this to put ``queue_trans``, ``get_trans_result`` and
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``transmit`` functions into the IRAM to avoid possible cache miss.
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During unit test, this is enabled to measure the ideal case of api.
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config SPI_MASTER_ISR_IN_IRAM
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bool "Place SPI master ISR function into IRAM"
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default y
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help
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Place the SPI master ISR in to IRAM to avoid possible cache miss.
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Also you can forbid the ISR being disabled during flash writing
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access, by add ESP_INTR_FLAG_IRAM when initializing the driver.
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config SPI_SLAVE_IN_IRAM
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bool "Place transmitting functions of SPI slave into IRAM"
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default n
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select SPI_SLAVE_ISR_IN_IRAM
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help
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Normally only the ISR of SPI slave is placed in the IRAM, so that it
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can work without the flash when interrupt is triggered.
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For other functions, there's some possibility that the flash cache
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miss when running inside and out of SPI functions, which may increase
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the interval of SPI transactions.
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Enable this to put ``queue_trans``, ``get_trans_result`` and
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``transmit`` functions into the IRAM to avoid possible cache miss.
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config SPI_SLAVE_ISR_IN_IRAM
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bool "Place SPI slave ISR function into IRAM"
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default y
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help
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Place the SPI slave ISR in to IRAM to avoid possible cache miss.
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Also you can forbid the ISR being disabled during flash writing
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access, by add ESP_INTR_FLAG_IRAM when initializing the driver.
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endmenu # SPI Configuration
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endmenu # Driver configurations
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