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fdf983e0c4
The SPI bus lock on SPI1 introduces two side effects:
1. The device lock for the main flash requires the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` to be selected, however this
option is disabled by default in earlier IDF versions. Some developers
may find their project cannot be built by their old sdkconfig files.
2. Usually we don't need the lock on the SPI1 bus, due to it's
restrictions. However the overhead still exists in this case, the IRAM
cost for static version of semaphore functions, and the time cost when
getting and releasing the lock.
This commit:
1. Add a CONFIG_SPI_FLASH_BYPASS_MAIN_LOCK option, which will forbid the
space cost, as well as the initialization of the main bus lock.
2. When the option is not selected, the bus lock is used, the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` will be selected explicitly.
3. Revert default value of `CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION`
to `n`.
introduced in 49a48644e4.
Closes https://github.com/espressif/esp-idf/issues/5046
33 lines
1.2 KiB
Plaintext
33 lines
1.2 KiB
Plaintext
menu "Example Configuration"
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config EXAMPLE_USE_SPI1_PINS
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bool "The example uses SPI1 shared pins for EEPROM connection"
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default n
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depends on SPI_FLASH_SHARE_SPI1_BUS
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help
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Enable this option will make the EEPROM use SPI1 pins, which is shared with the main
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flash chip.
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Currently this example hasn't supported SPI1 pins on other chips yet.
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config EXAMPLE_INTR_USED
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bool "Use the interrupt to detect the eeprom busy"
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default y
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depends on !EXAMPLE_USE_SPI1_PINS
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help
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Enable this option will allow the example to be blocked while the EEPROM is working
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in progress, and unblocked by GPIO interrupt. Otherwise the example will keep polling
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until the EEPROM is idle.
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config EXAMPLE_5V_COMMANDS
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bool "The EEPROM is supplied by 5V power"
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default n
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help
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The Erase_All and Write_All commands of EEPROM are only supported when EEPROM is
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supplied by 5V power. Enable this to use those two commands.
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But please note that ESP chips don't support 5V IO, you need to add external
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level-shifting circuits between ESP chip to the EEPROM.
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endmenu
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