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https://github.com/espressif/esp-idf.git
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40f3bc2e57
- Support SOC ROOT clock source switch - Support CPU frequency change - Support RTC SLOW clock source switch - Support RTC SLOW clock + RC FAST calibration - Remove FPGA build
86 lines
2.4 KiB
C
86 lines
2.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/clkout_channel.h"
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#include "hal/assert.h"
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#include "hal/clk_tree_hal.h"
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#include "hal/clk_tree_ll.h"
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#include "hal/gpio_ll.h"
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#include "hal/log.h"
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#include "sdkconfig.h"
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uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
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{
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switch (cpu_clk_src) {
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case SOC_CPU_CLK_SRC_XTAL:
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return clk_hal_xtal_get_freq_mhz();
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case SOC_CPU_CLK_SRC_PLL_F160M:
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return CLK_LL_PLL_160M_FREQ_MHZ;
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case SOC_CPU_CLK_SRC_PLL_F240M:
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return CLK_LL_PLL_240M_FREQ_MHZ;
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case SOC_CPU_CLK_SRC_RC_FAST:
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return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
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default:
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// Unknown CPU_CLK mux input
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HAL_ASSERT(false);
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return 0;
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}
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}
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uint32_t clk_hal_cpu_get_freq_hz(void)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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uint32_t divider = clk_ll_cpu_get_divider();
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return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider;
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}
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uint32_t clk_hal_ahb_get_freq_hz(void)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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uint32_t divider = clk_ll_ahb_get_divider();
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return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider;
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}
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uint32_t clk_hal_apb_get_freq_hz(void)
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{
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return clk_hal_ahb_get_freq_hz() / clk_ll_apb_get_divider();
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}
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uint32_t clk_hal_lp_slow_get_freq_hz(void)
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{
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switch (clk_ll_rtc_slow_get_src()) {
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case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
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return SOC_CLK_RC_SLOW_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
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return SOC_CLK_XTAL32K_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW:
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return SOC_CLK_OSC_SLOW_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_RC32K:
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return SOC_CLK_RC32K_FREQ_APPROX;
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default:
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// Unknown RTC_SLOW_CLK mux input
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HAL_ASSERT(false);
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return 0;
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}
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}
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uint32_t clk_hal_xtal_get_freq_mhz(void)
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{
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uint32_t freq = clk_ll_xtal_get_freq_mhz();
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HAL_ASSERT(freq == SOC_XTAL_FREQ_48M || freq == SOC_XTAL_FREQ_40M);
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return freq;
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}
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void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
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{
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gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
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}
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void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
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{
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gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
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}
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