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https://github.com/espressif/esp-idf.git
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2b52f7f696
In psram timing tuning driver, we rely on psram read and write functions defined in `spi_timing_config.c`. If we don't do buffer reset (clear to 0), the function may untouch the buffer, which will keep last time value (since we reuse the buffer). Therefore, if the first read is expected, but next few reads didn't modify the buffer content, we will still see the expected data. These functions relies on `esp_rom_opiflash_exec_cmd`.
221 lines
10 KiB
C
221 lines
10 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "string.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_types.h"
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#include "esp_log.h"
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#include "soc/spi_mem_reg.h"
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#include "spi_timing_config.h"
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#define OPI_PSRAM_SYNC_READ 0x0000
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#define OPI_PSRAM_SYNC_WRITE 0x8080
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#define OCT_PSRAM_RD_DUMMY_NUM (2*(10-1))
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#define OCT_PSRAM_WR_DUMMY_NUM (2*(5-1))
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/////////////////////////////////////////TIMING TUNING IS NEEDED//////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////
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#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING //If one of the FLASH / PSRAM or both of them need timing tuning, we should build following code
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spi_timing_config_core_clock_t IRAM_ATTR spi_timing_config_get_core_clock(void)
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{
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switch (SPI_TIMING_CORE_CLOCK_MHZ) {
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case 80:
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return SPI_TIMING_CONFIG_CORE_CLOCK_80M;
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case 120:
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return SPI_TIMING_CONFIG_CORE_CLOCK_120M;
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case 160:
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return SPI_TIMING_CONFIG_CORE_CLOCK_160M;
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case 240:
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return SPI_TIMING_CONFIG_CORE_CLOCK_240M;
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default:
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abort();
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}
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}
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void IRAM_ATTR spi_timing_config_set_core_clock(uint8_t spi_num, spi_timing_config_core_clock_t core_clock)
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{
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uint32_t reg_val = 0;
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switch (core_clock) {
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case SPI_TIMING_CONFIG_CORE_CLOCK_80M:
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reg_val = 0;
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break;
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case SPI_TIMING_CONFIG_CORE_CLOCK_120M:
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reg_val = 1;
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break;
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case SPI_TIMING_CONFIG_CORE_CLOCK_160M:
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reg_val = 2;
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break;
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case SPI_TIMING_CONFIG_CORE_CLOCK_240M:
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reg_val = 3;
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break;
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default:
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abort();
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}
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REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(spi_num), SPI_MEM_CORE_CLK_SEL, reg_val);
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}
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//-------------------------------------FLASH timing tuning-------------------------------------//
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void IRAM_ATTR spi_timing_config_set_flash_clock(uint8_t spi_num, uint32_t freqdiv)
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{
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assert(freqdiv > 0);
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if (freqdiv == 1) {
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WRITE_PERI_REG(SPI_MEM_CLOCK_REG(spi_num), SPI_MEM_CLK_EQU_SYSCLK);
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} else {
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uint32_t freqbits = (((freqdiv - 1) << SPI_MEM_CLKCNT_N_S)) | (((freqdiv / 2 - 1) << SPI_MEM_CLKCNT_H_S)) | ((freqdiv - 1) << SPI_MEM_CLKCNT_L_S);
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WRITE_PERI_REG(SPI_MEM_CLOCK_REG(spi_num), freqbits);
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}
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}
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void IRAM_ATTR spi_timing_config_flash_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num)
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{
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uint32_t reg_val = 0;
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reg_val = (REG_READ(SPI_MEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_DIN0_MODE_M | SPI_MEM_DIN1_MODE_M | SPI_MEM_DIN2_MODE_M | SPI_MEM_DIN3_MODE_M | SPI_MEM_DIN4_MODE_M | SPI_MEM_DIN5_MODE_M | SPI_MEM_DIN6_MODE_M | SPI_MEM_DIN7_MODE_M | SPI_MEM_DINS_MODE_M)))
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| (din_mode << SPI_MEM_DIN0_MODE_S) | (din_mode << SPI_MEM_DIN1_MODE_S) | (din_mode << SPI_MEM_DIN2_MODE_S) | (din_mode << SPI_MEM_DIN3_MODE_S)
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| (din_mode << SPI_MEM_DIN4_MODE_S) | (din_mode << SPI_MEM_DIN5_MODE_S) | (din_mode << SPI_MEM_DIN6_MODE_S) | (din_mode << SPI_MEM_DIN7_MODE_S) | (din_mode << SPI_MEM_DINS_MODE_S);
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REG_WRITE(SPI_MEM_DIN_MODE_REG(spi_num), reg_val);
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reg_val = (REG_READ(SPI_MEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_DIN0_NUM_M | SPI_MEM_DIN1_NUM_M | SPI_MEM_DIN2_NUM_M | SPI_MEM_DIN3_NUM_M | SPI_MEM_DIN4_NUM_M | SPI_MEM_DIN5_NUM_M | SPI_MEM_DIN6_NUM_M | SPI_MEM_DIN7_NUM_M | SPI_MEM_DINS_NUM_M)))
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| (din_num << SPI_MEM_DIN0_NUM_S) | (din_num << SPI_MEM_DIN1_NUM_S) | (din_num << SPI_MEM_DIN2_NUM_S) | (din_num << SPI_MEM_DIN3_NUM_S)
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| (din_num << SPI_MEM_DIN4_NUM_S) | (din_num << SPI_MEM_DIN5_NUM_S) | (din_num << SPI_MEM_DIN6_NUM_S) | (din_num << SPI_MEM_DIN7_NUM_S) | (din_num << SPI_MEM_DINS_NUM_S);
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REG_WRITE(SPI_MEM_DIN_NUM_REG(spi_num), reg_val);
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}
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void IRAM_ATTR spi_timing_config_flash_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
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{
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if (extra_dummy > 0) {
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SET_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_M);
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SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
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SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
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} else {
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CLEAR_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_M);
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SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, 0,
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SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
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}
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}
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//-------------------------------------PSRAM timing tuning-------------------------------------//
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void IRAM_ATTR spi_timing_config_set_psram_clock(uint8_t spi_num, uint32_t freqdiv)
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{
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if (freqdiv == 1) {
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WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
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} else {
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uint32_t freqbits = (((freqdiv-1)<<SPI_MEM_SCLKCNT_N_S)) | (((freqdiv/2-1)<<SPI_MEM_SCLKCNT_H_S)) | ((freqdiv-1)<<SPI_MEM_SCLKCNT_L_S);
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WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
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}
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}
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void IRAM_ATTR spi_timing_config_psram_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num)
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{
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uint32_t reg_val = 0;
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reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_MODE_M | SPI_MEM_SPI_SMEM_DIN1_MODE_M | SPI_MEM_SPI_SMEM_DIN2_MODE_M | SPI_MEM_SPI_SMEM_DIN3_MODE_M | SPI_MEM_SPI_SMEM_DIN4_MODE_M | SPI_MEM_SPI_SMEM_DIN5_MODE_M | SPI_MEM_SPI_SMEM_DIN6_MODE_M | SPI_MEM_SPI_SMEM_DIN7_MODE_M | SPI_MEM_SPI_SMEM_DINS_MODE_M)))
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| (din_mode << SPI_MEM_SPI_SMEM_DIN0_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN1_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN2_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN3_MODE_S)
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| (din_mode << SPI_MEM_SPI_SMEM_DIN4_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN5_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN6_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN7_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DINS_MODE_S);
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REG_WRITE(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num), reg_val);
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reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_NUM_M | SPI_MEM_SPI_SMEM_DIN1_NUM_M | SPI_MEM_SPI_SMEM_DIN2_NUM_M | SPI_MEM_SPI_SMEM_DIN3_NUM_M | SPI_MEM_SPI_SMEM_DIN4_NUM_M | SPI_MEM_SPI_SMEM_DIN5_NUM_M | SPI_MEM_SPI_SMEM_DIN6_NUM_M | SPI_MEM_SPI_SMEM_DIN7_NUM_M | SPI_MEM_SPI_SMEM_DINS_NUM_M)))
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| (din_num << SPI_MEM_SPI_SMEM_DIN0_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN1_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN2_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN3_NUM_S)
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| (din_num << SPI_MEM_SPI_SMEM_DIN4_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN5_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN6_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN7_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DINS_NUM_S);
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REG_WRITE(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num), reg_val);
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}
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void IRAM_ATTR spi_timing_config_psram_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
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{
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if (extra_dummy > 0) {
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SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CALI_M);
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SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
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SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
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} else {
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CLEAR_PERI_REG_MASK(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CALI_M);
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SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, 0,
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SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
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}
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}
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//-------------------------------------------FLASH/PSRAM Read/Write------------------------------------------//
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void IRAM_ATTR spi_timing_config_flash_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
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{
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#if CONFIG_ESPTOOLPY_OCT_FLASH
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// note that in spi_flash_read API, there is a wait-idle stage, since flash can only be read in idle state.
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// but after we change the timing settings, we might not read correct idle status via RDSR.
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// so, here we should use a read API that won't check idle status.
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for (int i = 0; i < 16; i++) {
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REG_WRITE(SPI_MEM_W0_REG(1) + i*4, 0);
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}
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esp_rom_opiflash_read_raw(addr, buf, len);
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#else
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abort();
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#endif
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}
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static void IRAM_ATTR s_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
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{
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#if CONFIG_SPIRAM_MODE_OCT
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esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_OPI_DTR_MODE,
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OPI_PSRAM_SYNC_WRITE, 16,
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addr, 32,
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OCT_PSRAM_WR_DUMMY_NUM,
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buf, 8 * len,
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NULL, 0,
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BIT(1),
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false);
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#else
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abort();
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#endif
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}
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static void IRAM_ATTR s_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
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{
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#if CONFIG_SPIRAM_MODE_OCT
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for (int i = 0; i < 16; i++) {
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REG_WRITE(SPI_MEM_W0_REG(1) + i*4, 0);
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}
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esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_OPI_DTR_MODE,
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OPI_PSRAM_SYNC_READ, 16,
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addr, 32,
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OCT_PSRAM_RD_DUMMY_NUM,
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NULL, 0,
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buf, 8 * len,
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BIT(1),
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false);
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#else
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abort();
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#endif
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}
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static void IRAM_ATTR s_psram_execution(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len, bool is_read)
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{
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while (len) {
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uint32_t length = MIN(len, 32);
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if (is_read) {
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s_psram_read_data(1, buf, addr, length);
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} else {
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s_psram_write_data(1, buf, addr, length);
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}
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addr += length;
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buf += length;
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len -= length;
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}
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}
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void IRAM_ATTR spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
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{
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s_psram_execution(spi_num, buf, addr, len, false);
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}
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void IRAM_ATTR spi_timing_config_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
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{
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s_psram_execution(spi_num, buf, addr, len, true);
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}
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#endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
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