mirror of
https://github.com/espressif/esp-idf.git
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142 lines
4.4 KiB
C
142 lines
4.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_cpu.h"
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#include "esp_intr_alloc.h"
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#include "esp_debug_helpers.h"
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#include "soc/periph_defs.h"
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#include "hal/crosscore_int_ll.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/portmacro.h"
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#if CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
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#include "esp_gdbstub.h"
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#endif
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#define REASON_YIELD BIT(0)
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#define REASON_FREQ_SWITCH BIT(1)
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#define REASON_PRINT_BACKTRACE BIT(2)
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#define REASON_GDB_CALL BIT(3)
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#define REASON_TWDT_ABORT BIT(4)
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static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
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static volatile uint32_t reason[portNUM_PROCESSORS];
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/*
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ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
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the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.
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*/
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static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
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{
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portYIELD_FROM_ISR();
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}
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static void IRAM_ATTR esp_crosscore_isr(void *arg) {
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uint32_t my_reason_val;
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//A pointer to the correct reason array item is passed to this ISR.
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volatile uint32_t *my_reason=arg;
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//Clear the interrupt first.
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crosscore_int_ll_clear_interrupt(esp_cpu_get_core_id());
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//Grab the reason and clear it.
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portENTER_CRITICAL_ISR(&reason_spinlock);
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my_reason_val=*my_reason;
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*my_reason=0;
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portEXIT_CRITICAL_ISR(&reason_spinlock);
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//Check what we need to do.
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if (my_reason_val & REASON_YIELD) {
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esp_crosscore_isr_handle_yield();
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}
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if (my_reason_val & REASON_FREQ_SWITCH) {
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/* Nothing to do here; the frequency switch event was already
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* handled by a hook in xtensa_vectors.S. Could be used in the future
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* to allow DFS features without the extra latency of the ISR hook.
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*/
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}
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#if CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
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if (my_reason_val & REASON_GDB_CALL) {
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update_breakpoints();
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}
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#endif // !CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
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if (my_reason_val & REASON_PRINT_BACKTRACE) {
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esp_backtrace_print(100);
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}
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#if CONFIG_ESP_TASK_WDT_EN
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if (my_reason_val & REASON_TWDT_ABORT) {
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extern void task_wdt_timeout_abort(bool);
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/* Called from a crosscore interrupt, thus, we are not the core that received
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* the TWDT interrupt, call the function with `false` as a parameter. */
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task_wdt_timeout_abort(false);
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}
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#endif // CONFIG_ESP_TASK_WDT_EN
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}
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//Initialize the crosscore interrupt on this core. Call this once
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//on each active core.
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void esp_crosscore_int_init(void) {
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portENTER_CRITICAL(&reason_spinlock);
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reason[esp_cpu_get_core_id()]=0;
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portEXIT_CRITICAL(&reason_spinlock);
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esp_err_t err __attribute__((unused)) = ESP_OK;
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#if portNUM_PROCESSORS > 1
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if (esp_cpu_get_core_id()==0) {
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err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
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} else {
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err = esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
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}
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#else
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err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
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#endif
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ESP_ERROR_CHECK(err);
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}
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static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) {
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assert(core_id<portNUM_PROCESSORS);
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//Mark the reason we interrupt the other CPU
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portENTER_CRITICAL_ISR(&reason_spinlock);
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reason[core_id] |= reason_mask;
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portEXIT_CRITICAL_ISR(&reason_spinlock);
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//Poke the other CPU.
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crosscore_int_ll_trigger_interrupt(core_id);
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}
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void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
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{
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esp_crosscore_int_send(core_id, REASON_YIELD);
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}
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void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
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{
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esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
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}
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void IRAM_ATTR esp_crosscore_int_send_gdb_call(int core_id)
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{
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esp_crosscore_int_send(core_id, REASON_GDB_CALL);
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}
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void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
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{
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esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
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}
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#if CONFIG_ESP_TASK_WDT_EN
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void IRAM_ATTR esp_crosscore_int_send_twdt_abort(int core_id) {
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esp_crosscore_int_send(core_id, REASON_TWDT_ABORT);
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}
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#endif // CONFIG_ESP_TASK_WDT_EN
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