Marius Vikhammer 9a6de4cb3e fix(panic): fixed cache error being reported as illegal instruction ... On riscv chips accessing cache mapped memory regions over the ibus would result in an illegal instructions exception triggering faster than the cache error interrupt/exception. Added a cache error check in the panic handler, if any cache errors are active the panic handler will now report a cache error, even if the trigger exception was a illegal instructions.		2023-12-04 10:49:00 +08:00
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port	compiler: replaced noreturn by __noreturn__ in header files	2023-05-11 16:07:45 +08:00
private/esp_private	fix(panic): fixed cache error being reported as illegal instruction	2023-12-04 10:49:00 +08:00
riscv	System: implement libunwind library for RISC-V backtracing	2023-05-15 11:19:03 +08:00
x86	System: implement libunwind library for RISC-V backtracing	2023-05-15 11:19:03 +08:00
esp_clk_internal.h	rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in	2022-05-24 22:59:41 +08:00