mirror of
https://github.com/espressif/esp-idf.git
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263 lines
8.6 KiB
C
263 lines
8.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "esp_log.h"
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#include "esp_err.h"
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#include "esp_rom_gpio.h"
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#include "esp32s3/rom/gpio.h"
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#include "esp32s3/rom/spi_flash.h"
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#include "esp32s3/rom/opi_flash.h"
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#include "esp_private/spi_flash_os.h"
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#include "opi_flash_private.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/io_mux_reg.h"
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#include "opi_flash_cmd_format_mxic.h"
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#define SPI_FLASH_SPI_CMD_WRCR2 0x72
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#define SPI_FLASH_SPI_CMD_RDSR 0x05
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#define SPI_FLASH_SPI_CMD_RDCR 0x15
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#define SPI_FLASH_SPI_CMD_WRSRCR 0x01
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/**
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* Supported Flash chip vendor id
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*/
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#define ESP_FLASH_CHIP_MXIC_OCT 0xC2
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const static char *TAG = "Octal Flash";
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// default value is rom_default_spiflash_legacy_flash_func
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extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
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extern int SPI_write_enable(void *spi);
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static uint32_t s_chip_id;
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static void s_register_rom_function(void)
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{
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static spiflash_legacy_funcs_t rom_func =
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{
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.read_sub_len = 32,
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.write_sub_len = 32,
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.unlock = esp_rom_opiflash_wait_idle,
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.erase_block = esp_rom_opiflash_erase_block_64k,
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.erase_sector = esp_rom_opiflash_erase_sector,
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.read = esp_rom_opiflash_read,
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.write = esp_rom_opiflash_write,
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.wait_idle = esp_rom_opiflash_wait_idle,
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.wren = esp_rom_opiflash_wren,
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.erase_area = esp_rom_opiflash_erase_area,
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};
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rom_spiflash_legacy_funcs = &rom_func;
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}
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#if CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP
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/*----------------------------------------------------------------------------------------------------
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MXIC Specific Functions
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-----------------------------------------------------------------------------------------------------*/
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static esp_err_t s_probe_mxic_chip(uint32_t chip_id, uint8_t *out_vendor_id)
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{
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if (chip_id >> 16 != ESP_FLASH_CHIP_MXIC_OCT) {
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return ESP_ERR_NOT_FOUND;
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}
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if (((chip_id >> 8) & 0xff) != 0x80) {
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ESP_EARLY_LOGE(TAG, "Detected MXIC Flash, but memory type is not Octal");
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return ESP_ERR_NOT_FOUND;
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}
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*out_vendor_id = ESP_FLASH_CHIP_MXIC_OCT;
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return ESP_OK;
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}
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// 0x00: SPI; 0x01: STR OPI; 0x02: DTR OPI
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static void s_set_flash_dtr_str_opi_mode(int spi_num, uint8_t val)
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{
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uint8_t cmd_len = 8;
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int addr_bit_len = 32;
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int dummy = 0;
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int data_bit_len = 8;
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SPI_write_enable(&g_rom_flashchip);
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//SPI command, WRCR2
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esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_FASTRD_MODE,
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SPI_FLASH_SPI_CMD_WRCR2, cmd_len,
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0, addr_bit_len,
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dummy,
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(uint8_t *)&val, data_bit_len,
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NULL, 0,
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ESP_ROM_OPIFLASH_SEL_CS0,
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false);
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}
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//To set the output driver strength
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static void s_set_flash_ouput_driver_strength(int spi_num, uint8_t strength)
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{
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uint16_t reg_val = 0;
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uint8_t sr_reg_val = 0;
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uint8_t cr_reg_val = 0;
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uint8_t cmd_len = 8;
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uint32_t addr = 0;
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int addr_bit_len = 0;
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int dummy = 0;
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int data_bit_len = 8;
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//Read
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//SPI command, RDSR
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esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_FASTRD_MODE,
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SPI_FLASH_SPI_CMD_RDSR, cmd_len,
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addr, addr_bit_len,
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dummy,
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NULL, 0,
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(uint8_t*)&sr_reg_val, data_bit_len,
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ESP_ROM_OPIFLASH_SEL_CS0,
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false);
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//SPI command, RDCR
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esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_FASTRD_MODE,
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SPI_FLASH_SPI_CMD_RDCR, cmd_len,
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addr, addr_bit_len,
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dummy,
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NULL, 0,
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(uint8_t*)&cr_reg_val, data_bit_len,
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ESP_ROM_OPIFLASH_SEL_CS0,
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false);
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//Modify
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reg_val = (((cr_reg_val & 0xf8) | strength) << 8) | sr_reg_val;
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//Write
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//SPI command, WRSR/WRCR
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data_bit_len = 16;
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SPI_write_enable(&g_rom_flashchip);
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esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_FASTRD_MODE,
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SPI_FLASH_SPI_CMD_WRSRCR, cmd_len,
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addr, addr_bit_len,
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dummy,
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(uint8_t*)®_val, data_bit_len,
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NULL, 0,
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ESP_ROM_OPIFLASH_SEL_CS0,
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false);
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}
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static void s_set_pin_drive_capability(uint8_t drv)
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{
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//flash clock
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REG_SET_FIELD(SPI_MEM_DATE_REG(0), SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV, 3);
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//cs0
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PIN_SET_DRV(IO_MUX_GPIO29_REG, 3);
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}
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static void s_flash_init_mxic(esp_rom_spiflash_read_mode_t mode)
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{
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static const esp_rom_opiflash_def_t opiflash_cmd_def_mxic = OPI_CMD_FORMAT_MXIC();
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esp_rom_opiflash_legacy_driver_init(&opiflash_cmd_def_mxic);
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esp_rom_spiflash_wait_idle(&g_rom_flashchip);
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// increase flash output driver strength
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s_set_flash_ouput_driver_strength(1, 7);
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// STR/DTR specific setting
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esp_rom_spiflash_wait_idle(&g_rom_flashchip);
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#if CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR
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s_set_pin_drive_capability(3);
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s_set_flash_dtr_str_opi_mode(1, 0x1);
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esp_rom_opiflash_cache_mode_config(mode, &rom_opiflash_cmd_def->cache_rd_cmd);
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esp_rom_spi_set_dtr_swap_mode(0, false, false);
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esp_rom_spi_set_dtr_swap_mode(1, false, false);
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#else //CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
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s_set_pin_drive_capability(3);
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s_set_flash_dtr_str_opi_mode(1, 0x2);
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esp_rom_opiflash_cache_mode_config(mode, &rom_opiflash_cmd_def->cache_rd_cmd);
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esp_rom_spi_set_dtr_swap_mode(0, true, true);
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esp_rom_spi_set_dtr_swap_mode(1, true, true);
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#endif
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esp_rom_opiflash_wait_idle();
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}
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#endif // #if CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP
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static void s_mxic_set_required_regs(uint32_t chip_id)
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{
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bool is_swap = false;
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#if CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
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is_swap = true;
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#else
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//STR mode does not need to enable ddr_swap registers
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#endif
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esp_rom_spi_set_dtr_swap_mode(0, is_swap, is_swap);
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esp_rom_spi_set_dtr_swap_mode(1, is_swap, is_swap);
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}
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/*----------------------------------------------------------------------------------------------------
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General Functions
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-----------------------------------------------------------------------------------------------------*/
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typedef struct opi_flash_func_t {
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esp_err_t (*probe)(uint32_t flash_id, uint8_t *out_vendor_id); //Function pointer for detecting Flash chip vendor
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void (*init)(esp_rom_spiflash_read_mode_t mode); //Function pointer for initialising certain Flash chips
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void (*regs_set)(uint32_t flash_id); //Function pointer for setting required registers, decided by certain flash chips.
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} opi_flash_func_t;
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#if CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP
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static const opi_flash_func_t opi_flash_func_mxic = {
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.probe = &s_probe_mxic_chip,
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.init = &s_flash_init_mxic,
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.regs_set = &s_mxic_set_required_regs,
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};
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#endif
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static const opi_flash_func_t *registered_chip_funcs[] = {
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#if CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP
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&opi_flash_func_mxic,
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#endif
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NULL,
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};
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//To check which Flash chip is used
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static const opi_flash_func_t **s_chip_func = NULL;
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esp_err_t esp_opiflash_init(uint32_t chip_id)
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{
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esp_err_t ret = ESP_FAIL;
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esp_rom_spiflash_read_mode_t mode;
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#if CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR
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mode = ESP_ROM_SPIFLASH_OPI_STR_MODE;
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#elif CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
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mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE;
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#else
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mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
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#endif
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const opi_flash_func_t **chip_func = ®istered_chip_funcs[0];
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uint8_t vendor_id = 0;
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while (*chip_func) {
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ret = (*chip_func)->probe(chip_id, &vendor_id);
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if (ret == ESP_OK) {
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// Detect this is the supported chip type
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s_chip_id = chip_id;
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(*chip_func)->init(mode);
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s_register_rom_function();
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break;
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}
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chip_func++;
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}
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s_chip_func = chip_func;
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if (ret != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "No detected Flash chip, please check the menuconfig to see if the chip is supported");
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abort();
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}
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return ESP_OK;
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}
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/**
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* Add Flash chip specifically required MSPI register settings here
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*/
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void esp_opiflash_set_required_regs(void)
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{
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(*s_chip_func)->regs_set(s_chip_id);
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}
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