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928859307f
Closes https://github.com/espressif/esp-idf/issues/13629 NMI interrupt level has been freed for all the Xtensa targets, making it possible for the main application to use it. An example has been added to show how to proceed.
48 lines
1.1 KiB
ArmAsm
48 lines
1.1 KiB
ArmAsm
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Unlicense OR CC0-1.0
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*/
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#include <xtensa/coreasm.h>
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#include "soc/gpio_reg.h"
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#include "example_gpio.h"
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.global nmi_triggered
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.section .bss
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nmi_triggered:
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.space 4
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/**
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* @brief This current ISR was called via `call0` instruction, so `a0` (return address)
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* was altered. Fortunately, `a0` was saved in EXCSAVE registers, restore it before
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* returning
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*/
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.section .iram1, "ax"
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.align 4
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.global xt_nmi
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.type xt_nmi, @function
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xt_nmi:
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addi sp, sp, -16
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s32i a3, sp, 0
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/* Set the interrupt flag to 1 */
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movi a0, nmi_triggered
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movi a3, 1
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s32i a3, a0, 0
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/* Set the GPIO level back to low to prevent triggering an interrupt again */
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movi a0, GPIO_OUT_W1TC_REG
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movi a3, 1 << EXAMPLE_GPIO_IN
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s32i a3, a0, 0
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/* Restore a3 and a0 before leaving*/
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l32i a3, sp, 0
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addi sp, sp, 16
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rsr a0, EXCSAVE + XCHAL_NMILEVEL
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/* Return from NMI, we need to specify the level */
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rfi XCHAL_NMILEVEL
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