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b2c074bb70
When porting an RTOS to the Xtensa architecture, there are a few files that
are common to all Xtensa RTOS ports. These files form the Xtensa RTOS porting
layer (e.g., "xtensa_vectors.S", "xtensa_context.S"). An Xtensa RTOS port is
expected to provide an RTOS specific "xtensa_rtos.h" header to interface with
the Xtensa RTOS porting layer.
Previously, the Xtensa RTOS porting layer files were placed in the FreeRTOS
component. This commit does the following:
1. Moves the Xtensa RTOS porting layer files from the `freertos` component to
the `xtensa` component. The following files were moved:
- xtensa_asm_utils.h
- xtensa_context.S
- xtensa_loadstore_handler.S
- xtensa_vectors.S
2. Refactored xtensa component include paths to separate Xtensa RTOS porting
layer headers.
- Xtensa HAL headers included via `#include <xtensa/...h>`
- Xtensa RTOS porting layer headers included via `#include <...h>`
Note: The xtensa files in the Amazon SMP FreeRTOS port are not moved/deleted in
this commit to ensure the moved files retain a clean diff history.
165 lines
6.1 KiB
C
165 lines
6.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
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*
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* SPDX-License-Identifier: MIT
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*
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* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
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*/
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/*
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* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
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*
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* This header contains definitions and macros for use primarily by Xtensa
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* RTOS assembly coded source files. It includes and uses the Xtensa hardware
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* abstraction layer (HAL) to deal with config specifics. It may also be
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* included in C source files.
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*
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* Edit this file to modify timer selection and to specify clock frequency and
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* tick duration to match timer interrupt to the real-time tick duration.
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*
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* If the RTOS has no timer interrupt, then there is no tick timer and the
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* clock frequency is irrelevant, so all of these macros are left undefined
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* and the Xtensa core configuration need not have a timer.
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*/
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#ifndef XTENSA_TIMER_H
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#define XTENSA_TIMER_H
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#ifdef __ASSEMBLER__
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#include <xtensa/coreasm.h>
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#endif
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include "xtensa_rtos.h" /* in case this wasn't included directly */
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/*
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Select timer to use for periodic tick, and determine its interrupt number
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and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
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in which case its validity is checked (it must exist in this core and must
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not be on a high priority interrupt - an error will be reported in invalid).
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Otherwise select the first low or medium priority interrupt timer available.
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*/
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#if XCHAL_NUM_TIMERS == 0
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#error "This Xtensa configuration is unsupported, it has no timers."
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#else
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#ifndef XT_TIMER_INDEX
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#if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 3
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#endif
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#endif
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#if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 2
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#endif
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#endif
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#if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 1
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#endif
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#endif
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#if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 0
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#endif
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#endif
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#endif
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#ifndef XT_TIMER_INDEX
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#error "There is no suitable timer in this Xtensa configuration."
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#endif
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#define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX)
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#define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
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#define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
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#define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM)
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#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
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#error "The timer selected by XT_TIMER_INDEX does not exist in this core."
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#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
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#error "The timer interrupt cannot be high priority (use medium or low)."
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#endif
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#endif /* XCHAL_NUM_TIMERS */
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/*
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Set processor clock frequency, used to determine clock divisor for timer tick.
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User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
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If using a supported board via the board-independent API defined in xtbsp.h,
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this may be left undefined and frequency and tick divisor will be computed
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and cached during run-time initialization.
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NOTE ON SIMULATOR:
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Under the Xtensa instruction set simulator, the frequency can only be estimated
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because it depends on the speed of the host and the version of the simulator.
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Also because it runs much slower than hardware, it is not possible to achieve
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real-time performance for most applications under the simulator. A frequency
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too low does not allow enough time between timer interrupts, starving threads.
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To obtain a more convenient but non-real-time tick duration on the simulator,
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compile with xt-xcc option "-DXT_SIMULATOR".
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Adjust this frequency to taste (it's not real-time anyway!).
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*/
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#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
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#define XT_CLOCK_FREQ configCPU_CLOCK_HZ
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#endif
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#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
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#error "XT_CLOCK_FREQ must be defined for the target platform."
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#endif
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/*
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Default number of timer "ticks" per second (default 100 for 10ms tick).
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RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
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User may redefine this to an optimal value for the application, either by
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editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
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"-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
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*/
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#ifndef XT_TICK_PER_SEC
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#define XT_TICK_PER_SEC configTICK_RATE_HZ /* 10 ms tick = 100 ticks per second */
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#endif
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/*
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Derivation of clock divisor for timer tick and interrupt (one per tick).
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*/
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#ifdef XT_CLOCK_FREQ
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#define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
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#endif
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#ifndef __ASSEMBLER__
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extern unsigned _xt_tick_divisor;
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extern void _xt_tick_divisor_init(void);
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#endif
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#endif /* XTENSA_TIMER_H */
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