mirror of
https://github.com/espressif/esp-idf.git
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200f69e6eb
modem retention: Support esp32c6 wifi MAC and baseband sleep retention sleep_modem: wifi MAC modem wakeup protect in modem state before PMU trigger sleep enable request sleep modem: provide a interface to get whether the Modem power domain is allowed to power off during sleep add i2c_ana master header file to project auto beacon: release PMU's lock on root clock source (it is locked in the PLL) wifi receiving beacon frame in PMU modem state strongly depends on the BBPLL clock, PMU will forcibly lock the root clock source as PLL, when the root clock source of the software system is selected as PLL, we need to release the root clock source locking. When it is judged that the PLL is locked by PMU after wakeing up from the PMU modem state, switch the root clock source to the PLL in the sleep process (a critical section). auto beacon: fix the failure to receive broadcast/multicast frames in modem state When the multicast field in the beacon frame received in the PMU modem state is True, the PMU switches to the PMU active state (the PMU waits for the HP LDO to stabilize and then restores the MAC context) and starts to receive broadcast/multicast frames (Broadcast/Multicast frames will be sent after a minimum delay of 48 us after the beacon frame), because the PMU waits for the HP LDO to stabilize too long (~154 us), which will cause broadcast/multicast frame reception to be missed. auto beacon: select the PLL clock source as the REGDMA backup clock source when the PMU switches to ACTIVE from MODEM state update Digital Peripheral (M2A switch) REGDMA restore time parameter auto beacon: fix the issue that only channel 1 can connect to AP in modem state
83 lines
4.2 KiB
C
83 lines
4.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DR_REG_PLIC_MX_BASE 0x20001000
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#define DR_REG_PLIC_UX_BASE 0x20001400
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#define DR_REG_CLINT_M_BASE 0x20001800
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#define DR_REG_CLINT_U_BASE 0x20001C00
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#define DR_REG_UART_BASE 0x60000000
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#define DR_REG_UART1_BASE 0x60001000
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#define DR_REG_SPI0_BASE 0x60002000
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#define DR_REG_SPI1_BASE 0x60003000
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#define DR_REG_I2C_EXT_BASE 0x60004000
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#define DR_REG_UHCI0_BASE 0x60005000
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#define DR_REG_RMT_BASE 0x60006000
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#define DR_REG_LEDC_BASE 0x60007000
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#define DR_REG_TIMERGROUP0_BASE 0x60008000
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#define DR_REG_TIMERGROUP1_BASE 0x60009000
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#define DR_REG_SYSTIMER_BASE 0x6000A000
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#define DR_REG_TWAI0_BASE 0x6000B000
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#define DR_REG_I2S_BASE 0x6000C000
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#define DR_REG_TWAI1_BASE 0x6000D000
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#define DR_REG_APB_SARADC_BASE 0x6000E000
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#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000
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#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000
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#define DR_REG_ATOMIC_BASE 0x60011000
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#define DR_REG_PCNT_BASE 0x60012000
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#define DR_REG_SOC_ETM_BASE 0x60013000
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#define DR_REG_MCPWM_BASE 0x60014000
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#define DR_REG_PARL_IO_BASE 0x60015000
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#define DR_REG_HINF_BASE 0x60016000
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#define DR_REG_SLC_BASE 0x60017000
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#define DR_REG_SLCHOST_BASE 0x60018000
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#define DR_REG_PVT_MONITOR_BASE 0x60019000
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#define DR_REG_GDMA_BASE 0x60080000
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#define DR_REG_SPI2_BASE 0x60081000
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#define DR_REG_AES_BASE 0x60088000
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#define DR_REG_SHA_BASE 0x60089000
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#define DR_REG_RSA_BASE 0x6008A000
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#define DR_REG_ECC_MULT_BASE 0x6008B000
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#define DR_REG_DS_BASE 0x6008C000
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#define DR_REG_HMAC_BASE 0x6008D000
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#define DR_REG_IO_MUX_BASE 0x60090000
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#define DR_REG_GPIO_BASE 0x60091000
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#define DR_REG_GPIO_EXT_BASE 0x60091f00 //ESP32C6-TODO
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#define DR_REG_MEM_MONITOR_BASE 0x60092000
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#define DR_REG_PAU_BASE 0x60093000
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#define DR_REG_HP_SYSTEM_BASE 0x60095000
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#define DR_REG_PCR_BASE 0x60096000
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#define DR_REG_TEE_BASE 0x60098000
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#define DR_REG_HP_APM_BASE 0x60099000
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#define DR_REG_LP_APM0_BASE 0x60099800
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#define DR_REG_MISC_BASE 0x6009F000
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#define DR_REG_I2C_ANA_MST_BASE 0x600AF800
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#define DR_REG_PMU_BASE 0x600B0000
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#define DR_REG_LP_CLKRST_BASE 0x600B0400
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#define DR_REG_EFUSE_BASE 0x600B0800
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#define DR_REG_LP_TIMER_BASE 0x600B0C00
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#define DR_REG_LP_AON_BASE 0x600B1000
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#define DR_REG_LP_UART_BASE 0x600B1400
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#define DR_REG_LP_I2C_BASE 0x600B1800
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#define DR_REG_LP_WDT_BASE 0x600B1C00
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#define DR_REG_LP_IO_BASE 0x600B2000
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#define DR_REG_LP_I2C_ANA_MST_BASE 0x600B2400
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#define DR_REG_LPPERI_BASE 0x600B2800
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#define DR_REG_LP_ANALOG_PERI_BASE 0x600B2C00
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#define DR_REG_LP_TEE_BASE 0x600B3400
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#define DR_REG_LP_APM_BASE 0x600B3800
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#define DR_REG_OPT_DEBUG_BASE 0x600B3C00
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#define DR_REG_TRACE_BASE 0x600C0000
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#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000
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#define DR_REG_CPU_BUS_MONITOR_BASE 0x600C2000
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#define DR_REG_INTPRI_BASE 0x600C5000
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#define DR_REG_EXTMEM_BASE 0x600C8000
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#define PWDET_CONF_REG 0x600A8010
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