esp-idf/components/esp_hw_support/Kconfig

menu "Hardware Settings"
    menu "MAC Config"
        config ESP_MAC_ADDR_UNIVERSE_WIFI_STA
            bool

        config ESP_MAC_ADDR_UNIVERSE_WIFI_AP
            bool

        config ESP_MAC_ADDR_UNIVERSE_BT
            bool

        config ESP_MAC_ADDR_UNIVERSE_ETH
            bool

            # Insert chip-specific MAC config
            rsource "./port/$IDF_TARGET/Kconfig.mac"

        config ESP_MAC_IGNORE_MAC_CRC_ERROR
            bool "Ignore MAC CRC error (not recommended)"
            depends on IDF_TARGET_ESP32
            default n
            help
                If you have an invalid MAC CRC (ESP_ERR_INVALID_CRC) problem
                and you still want to use this chip, you can enable this option to bypass such an error.
                This applies to both MAC_FACTORY and CUSTOM_MAC efuses.
    endmenu

    menu "Sleep Config"
        # This is here since this option affect behavior of esp_light_sleep_start
        # regardless of power management configuration.
        config ESP_SLEEP_POWER_DOWN_FLASH
            bool "Power down flash in light sleep when there is no SPIRAM"
            depends on !SPIRAM
            default n
            help
                If enabled, chip will try to power down flash as part of esp_light_sleep_start(), which costs
                more time when chip wakes up. Can only be enabled if there is no SPIRAM configured.

                This option will power down flash under a strict but relatively safe condition. Also, it is possible to
                power down flash under a relaxed condition by using esp_sleep_pd_config() to set ESP_PD_DOMAIN_VDDSDIO
                to ESP_PD_OPTION_OFF. It should be noted that there is a risk in powering down flash, you can refer
                `ESP-IDF Programming Guide/API Reference/System API/Sleep Modes/Power-down of Flash` for more details.

        config ESP_SLEEP_RTC_BUS_ISO_WORKAROUND
            bool
            default y if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3

        config ESP_SLEEP_GPIO_RESET_WORKAROUND
            bool "light sleep GPIO reset workaround"
            default y if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32H2
            select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE
            help
                esp32c3, esp32s3 and esp32h2 will reset at wake-up if GPIO is received a small electrostatic
                pulse during light sleep, with specific condition

                - GPIO needs to be configured as input-mode only
                - The pin receives a small electrostatic pulse, and reset occurs when the pulse
                  voltage is higher than 6 V

                For GPIO set to input mode only, it is not a good practice to leave it open/floating,
                The hardware design needs to controlled it with determined supply or ground voltage
                is necessary.

                This option provides a software workaround for this issue. Configure to isolate all
                GPIO pins in sleep state.

        config ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND
            bool "PSRAM leakage current workaround in light sleep"
            depends on SPIRAM
            default y
            help
                When the CS pin of SPIRAM is not pulled up, the sleep current will
                increase during light sleep. If the CS pin of SPIRAM has an external
                pull-up, you do not need to select this option, otherwise, you
                should enable this option.

        config ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
            bool "Flash leakage current workaround in light sleep"
            default y
            help
                When the CS pin of Flash is not pulled up, the sleep current will
                increase during light sleep. If the CS pin of Flash has an external
                pull-up, you do not need to select this option, otherwise, you
                should enable this option.

        config ESP_SLEEP_MSPI_NEED_ALL_IO_PU
            bool "All pins of mspi need pull up"
            depends on ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND || ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
            default y if IDF_TARGET_ESP32S3
            help
                To reduce leakage current, some types of SPI Flash/RAM only need to pull up the CS pin
                during light sleep. But there are also some kinds of SPI Flash/RAM that need to pull up
                all pins. It depends on the SPI Flash/RAM chip used.

        config ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS
            bool "Allow to enable internal pull-up/downs for the Deep-Sleep wakeup IOs"
            default y
            help
                When using rtc gpio wakeup source during deepsleep without external pull-up/downs, you may want to
                make use of the internal ones.
    endmenu

    menu "ESP_SLEEP_WORKAROUND"
        # No visible menu/configs for workaround
        visible if 0
        config ESP_SLEEP_SYSTIMER_STALL_WORKAROUND
            bool "ESP32C3 SYSTIMER Stall Issue Workaround"
            depends on IDF_TARGET_ESP32C3
            help
                Its not able to stall ESP32C3 systimer in sleep.
                To fix related RTOS TICK issue, select it to disable related systimer during sleep.
                TODO: IDF-7036
    endmenu

    menu "RTC Clock Config"
        # This is used for configure the RTC clock.
        config RTC_CLOCK_BBPLL_POWER_ON_WITH_USB
            bool "Keep BBPLL clock always work"
            depends on ESP_CONSOLE_USB_SERIAL_JTAG || ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
            default y
            help
                When software switches the CPU clock source from BBPLL clock to XTAL, usually the BBPLL will be
                switched off. This helps to save some power consumption in sleep modes. However this may also happen
                during the software reset, resulting in the inactive (disconnected from host) of the USB_SERIAL_JTAG
                device during software reset.

                When USB_SERIAL_JTAG is being used, whether to turn off the clock source during software reset and in
                sleep modes is determined by RTC_CLOCK_BBPLL_POWER_ON_WITH_USB.

                  - When RTC_CLOCK_BBPLL_POWER_ON_WITH_USB is enabled, the clock will be kept, so that the
                    USB_SERIAL_JTAG will keep alive during software reset. The side-effect is the increasing of power
                    consumption during sleep modes, even though USB_SERIAL_JTAG will not work in sleep modes.

                  - When RTC_CLOCK_BBPLL_POWER_ON_WITH_USB is disabled, the clock will be turned off. USB_SERIAL_JTAG
                    will be inactive during software reset and in sleep modes. This saves some power consumption in
                    sleep modes.

                When USB_SERIAL_JTAG is not being used, software will always turn off BBPLL regardless of
                RTC_CLOCK_BBPLL_POWER_ON_WITH_USB is set or not.
    endmenu
endmenu