mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
e09d50d244
1) In the ESP32-P4 SoC, we have an eFuse to disable the MSPI access
when in download mode. This commit adds relevant soc cap for esp32p4
chip.
2) Added FE related soc caps
3) Removed unwanted cap from soc_caps
4) esp_hw_support: Enable flash encryption related ll APIs for esp32p4
152 lines
4.1 KiB
C
152 lines
4.1 KiB
C
/*
|
|
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
/*******************************************************************************
|
|
* NOTICE
|
|
* The ll is not public api, don't use in application code.
|
|
* See readme.md in hal/include/hal/readme.md
|
|
******************************************************************************/
|
|
|
|
// The Lowlevel layer for SPI Flash Encryption.
|
|
|
|
#include <stdbool.h>
|
|
#include <string.h>
|
|
#include "soc/hp_system_reg.h"
|
|
#include "soc/spi_mem_reg.h"
|
|
#include "soc/soc.h"
|
|
#include "soc/soc_caps.h"
|
|
#include "hal/assert.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
/// Choose type of chip you want to encrypt manully
|
|
typedef enum
|
|
{
|
|
FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
|
|
PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
|
|
} flash_encrypt_ll_type_t;
|
|
|
|
/**
|
|
* Enable the flash encryption function under spi boot mode and download boot mode.
|
|
*/
|
|
static inline void spi_flash_encrypt_ll_enable(void)
|
|
{
|
|
REG_SET_BIT(HP_SYSTEM_CRYPTO_CTRL_REG,
|
|
HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT |
|
|
HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT);
|
|
}
|
|
|
|
/*
|
|
* Disable the flash encryption mode.
|
|
*/
|
|
static inline void spi_flash_encrypt_ll_disable(void)
|
|
{
|
|
REG_CLR_BIT(HP_SYSTEM_CRYPTO_CTRL_REG,
|
|
HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT);
|
|
}
|
|
|
|
/**
|
|
* Choose type of chip you want to encrypt manully
|
|
*
|
|
* @param type The type of chip to be encrypted
|
|
*
|
|
* @note The hardware currently support flash encryption.
|
|
*/
|
|
static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
|
|
{
|
|
// Our hardware only support flash encryption
|
|
HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
|
|
REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_MEM_SPI_XTS_DESTINATION, type);
|
|
}
|
|
|
|
/**
|
|
* Configure the data size of a single encryption.
|
|
*
|
|
* @param block_size Size of the desired block.
|
|
*/
|
|
static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
|
|
{
|
|
// Desired block should not be larger than the block size.
|
|
REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_MEM_SPI_XTS_LINESIZE, size >> 5);
|
|
}
|
|
|
|
/**
|
|
* Save 32-bit piece of plaintext.
|
|
*
|
|
* @param address the address of written flash partition.
|
|
* @param buffer Buffer to store the input data.
|
|
* @param size Buffer size.
|
|
*
|
|
*/
|
|
static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
|
|
{
|
|
uint32_t plaintext_offs = (address % SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX);
|
|
HAL_ASSERT(plaintext_offs + size <= SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX);
|
|
memcpy((void *)(SPI_MEM_XTS_PLAIN_BASE_REG(0) + plaintext_offs), buffer, size);
|
|
}
|
|
|
|
/**
|
|
* Copy the flash address to XTS_AES physical address
|
|
*
|
|
* @param flash_addr flash address to write.
|
|
*/
|
|
static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
|
|
{
|
|
REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS, flash_addr);
|
|
}
|
|
|
|
/**
|
|
* Start flash encryption
|
|
*/
|
|
static inline void spi_flash_encrypt_ll_calculate_start(void)
|
|
{
|
|
REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_MEM_SPI_XTS_TRIGGER, 1);
|
|
}
|
|
|
|
/**
|
|
* Wait for flash encryption termination
|
|
*/
|
|
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
|
|
{
|
|
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_SPI_XTS_STATE) == 0x1) {
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Finish the flash encryption and make encrypted result accessible to SPI.
|
|
*/
|
|
static inline void spi_flash_encrypt_ll_done(void)
|
|
{
|
|
REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_MEM_SPI_XTS_RELEASE);
|
|
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_SPI_XTS_STATE) != 0x3) {
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Set to destroy encrypted result
|
|
*/
|
|
static inline void spi_flash_encrypt_ll_destroy(void)
|
|
{
|
|
REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_MEM_SPI_XTS_DESTROY);
|
|
}
|
|
|
|
/**
|
|
* Check if is qualified to encrypt the buffer
|
|
*
|
|
* @param address the address of written flash partition.
|
|
* @param length Buffer size.
|
|
*/
|
|
static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
|
|
{
|
|
return ((address % length) == 0) ? true : false;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|