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4df3ff619e
- add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature
14 lines
375 B
C
14 lines
375 B
C
/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/soc.h"
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/* Since riscv does not replace mcause with "pseudo_reason" as it xtensa does
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* PANIC_RSN_* defined with original interrupt numbers to make it work in
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* common code
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*/
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#define PANIC_RSN_INTWDT_CPU0 ETS_INT_WDT_INUM
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