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57879e772d
There's two GDMA groups on ESP32P4, one is connected to AHB bus, and another one is connected AXI bus. We now have two seperate APIs for allocating DMA channels, depends on the bus type.
321 lines
15 KiB
Plaintext
321 lines
15 KiB
Plaintext
menu "Hardware Settings"
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menu "Chip revision"
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# Insert chip-specific HW config
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orsource "./port/$IDF_TARGET/Kconfig.hw_support"
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config ESP_REV_NEW_CHIP_TEST
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bool "Internal test mode"
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depends on IDF_CI_BUILD
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default n
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help
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For internal chip testing, a small number of new versions chips didn't
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update the version field in eFuse, you can enable this option to force the
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software recognize the chip version based on the rev selected in menuconfig.
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endmenu
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orsource "./port/$IDF_TARGET/Kconfig.spiram"
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menu "MAC Config"
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config ESP_MAC_ADDR_UNIVERSE_WIFI_STA
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bool
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config ESP_MAC_ADDR_UNIVERSE_WIFI_AP
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bool
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config ESP_MAC_ADDR_UNIVERSE_BT
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bool
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config ESP_MAC_ADDR_UNIVERSE_ETH
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bool
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config ESP_MAC_ADDR_UNIVERSE_IEEE802154
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bool
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config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_ONE
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bool
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config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO
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bool
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config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR
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bool
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# Insert chip-specific MAC config
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orsource "./port/$IDF_TARGET/Kconfig.mac"
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config ESP_MAC_IGNORE_MAC_CRC_ERROR
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bool "Ignore MAC CRC error (not recommended)"
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depends on IDF_TARGET_ESP32
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default n
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help
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If you have an invalid MAC CRC (ESP_ERR_INVALID_CRC) problem
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and you still want to use this chip, you can enable this option to bypass such an error.
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This applies to both MAC_FACTORY and CUSTOM_MAC efuses.
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endmenu
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menu "Sleep Config"
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# This is here since this option affect behavior of esp_light_sleep_start
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# regardless of power management configuration.
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config ESP_SLEEP_POWER_DOWN_FLASH
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bool "Power down flash in light sleep when there is no SPIRAM"
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depends on !SPIRAM
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default n
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help
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If enabled, chip will try to power down flash as part of esp_light_sleep_start(), which costs
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more time when chip wakes up. Can only be enabled if there is no SPIRAM configured.
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This option will power down flash under a strict but relatively safe condition. Also, it is possible to
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power down flash under a relaxed condition by using esp_sleep_pd_config() to set ESP_PD_DOMAIN_VDDSDIO
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to ESP_PD_OPTION_OFF. It should be noted that there is a risk in powering down flash, you can refer
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`ESP-IDF Programming Guide/API Reference/System API/Sleep Modes/Power-down of Flash` for more details.
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config ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
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bool "Pull-up Flash CS pin in light sleep"
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depends on !APP_BUILD_TYPE_PURE_RAM_APP && !ESP_SLEEP_POWER_DOWN_FLASH
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default y
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help
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All IOs will be set to isolate(floating) state by default during sleep.
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Since the power supply of SPI Flash is not lost during lightsleep, if its CS pin is recognized as
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low level(selected state) in the floating state, there will be a large current leakage, and the
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data in Flash may be corrupted by random signals on other SPI pins.
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Select this option will set the CS pin of Flash to PULL-UP state during sleep, but this will
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increase the sleep current about 10 uA.
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If you are developing with esp32xx modules, you must select this option, but if you are developing
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with chips, you can also pull up the CS pin of SPI Flash in the external circuit to save power
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consumption caused by internal pull-up during sleep.
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(!!! Don't deselect this option if you don't have external SPI Flash CS pin pullups.)
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config ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND
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bool "Pull-up PSRAM CS pin in light sleep"
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depends on SPIRAM
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default y
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help
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All IOs will be set to isolate(floating) state by default during sleep.
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Since the power supply of PSRAM is not lost during lightsleep, if its CS pin is recognized as
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low level(selected state) in the floating state, there will be a large current leakage, and the
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data in PSRAM may be corrupted by random signals on other SPI pins.
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Select this option will set the CS pin of PSRAM to PULL-UP state during sleep, but this will
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increase the sleep current about 10 uA.
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If you are developing with esp32xx modules, you must select this option, but if you are developing
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with chips, you can also pull up the CS pin of PSRAM in the external circuit to save power
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consumption caused by internal pull-up during sleep.
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(!!! Don't deselect this option if you don't have external PSRAM CS pin pullups.)
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config ESP_SLEEP_MSPI_NEED_ALL_IO_PU
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bool "Pull-up all SPI pins in light sleep"
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depends on !ESP_SLEEP_POWER_DOWN_FLASH \
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&& (ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND || ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND)
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default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3
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help
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To reduce leakage current, some types of SPI Flash/RAM only need to pull up the CS pin
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during light sleep. But there are also some kinds of SPI Flash/RAM that need to pull up
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all pins. It depends on the SPI Flash/RAM chip used.
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config ESP_SLEEP_RTC_BUS_ISO_WORKAROUND
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bool
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default y if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
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config ESP_SLEEP_GPIO_RESET_WORKAROUND
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bool "light sleep GPIO reset workaround"
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default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || \
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IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2
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select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE
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help
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esp32c2, esp32c3, esp32s3, esp32c6 and esp32h2 will reset at wake-up if GPIO is received
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a small electrostatic pulse during light sleep, with specific condition
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- GPIO needs to be configured as input-mode only
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- The pin receives a small electrostatic pulse, and reset occurs when the pulse
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voltage is higher than 6 V
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For GPIO set to input mode only, it is not a good practice to leave it open/floating,
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The hardware design needs to controlled it with determined supply or ground voltage
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is necessary.
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This option provides a software workaround for this issue. Configure to isolate all
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GPIO pins in sleep state.
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config ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY
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int "Extra delay in deep sleep wake stub (in us)"
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depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3
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default 2000
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range 0 5000
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help
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When the chip exits deep sleep, the CPU and the flash chip are powered on
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at the same time. CPU will run deep sleep stub first, and then
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proceed to load code from flash. Some flash chips need sufficient
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time to pass between power on and first read operation. By default,
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without any extra delay, this time is approximately 900us, although
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some flash chip types need more than that.
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By default extra delay is set to 2000us. When optimizing startup time
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for applications which require it, this value may be reduced.
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If you are seeing "flash read err, 1000" message printed to the
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console after deep sleep reset, try increasing this value.
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config ESP_SLEEP_CACHE_SAFE_ASSERTION
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bool "Check the cache safety of the sleep wakeup code in sleep process"
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default n
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help
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Enabling it will check the cache safety of the code before the flash power is ready after
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light sleep wakeup, and check PM_SLP_IRAM_OPT related code cache safety. This option is
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only for code quality inspection. Enabling it will increase the time overhead of entering
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and exiting sleep. It is not recommended to enable it in the release version.
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endmenu
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menu "ESP_SLEEP_WORKAROUND"
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# No visible menu/configs for workaround
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visible if 0
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config ESP_SLEEP_SYSTIMER_STALL_WORKAROUND
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bool "ESP32C3 SYSTIMER Stall Issue Workaround"
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depends on IDF_TARGET_ESP32C3
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help
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Its not able to stall ESP32C3 systimer in sleep.
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To fix related RTOS TICK issue, select it to disable related systimer during sleep.
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TODO: IDF-7036
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endmenu
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menu "RTC Clock Config"
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orsource "./port/$IDF_TARGET/Kconfig.rtc"
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endmenu
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menu "Peripheral Control"
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config PERIPH_CTRL_FUNC_IN_IRAM
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bool "Place peripheral control functions into IRAM"
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default n
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help
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Place peripheral control functions (e.g. periph_module_reset) into IRAM,
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so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
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endmenu
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menu "ETM Configuration"
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depends on SOC_ETM_SUPPORTED
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config ETM_ENABLE_DEBUG_LOG
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bool "Enable debug log"
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default n
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help
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Wether to enable the debug log message for ETM core driver.
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Note that, this option only controls the ETM related driver log, won't affect other drivers.
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endmenu # ETM Configuration
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menu "GDMA Configuration"
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depends on SOC_GDMA_SUPPORTED
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config GDMA_CTRL_FUNC_IN_IRAM
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bool "Place GDMA control functions into IRAM"
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default n
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help
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Place GDMA control functions (like start/stop/append/reset) into IRAM,
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so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
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Enabling this option can improve driver performance as well.
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config GDMA_ISR_IRAM_SAFE
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bool "GDMA ISR IRAM-Safe"
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default n
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help
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This will ensure the GDMA interrupt handler is IRAM-Safe, allow to avoid flash
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cache misses, and also be able to run whilst the cache is disabled.
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(e.g. SPI Flash write).
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config GDMA_ENABLE_DEBUG_LOG
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bool "Enable debug log"
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default n
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help
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Wether to enable the debug log message for GDMA driver.
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Note that, this option only controls the GDMA driver log, won't affect other drivers.
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endmenu # GDMA Configuration
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menu "Main XTAL Config"
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choice XTAL_FREQ_SEL
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prompt "Main XTAL frequency"
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default XTAL_FREQ_40 if SOC_XTAL_SUPPORT_40M
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help
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This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target.
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The selected value MUST reflect the frequency of the given hardware.
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Note: The XTAL_FREQ_AUTO option allows the ESP target to automatically estimating XTAL clock's
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operating frequency. However, this feature is only supported on the ESP32. The ESP32 uses the
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internal 8MHZ as a reference when estimating. Due to the internal oscillator's frequency being
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temperature dependent, usage of the XTAL_FREQ_AUTO is not recommended in applications that operate
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in high ambient temperatures or use high-temperature qualified chips and modules.
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config XTAL_FREQ_24
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depends on SOC_XTAL_SUPPORT_24M
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bool "24 MHz"
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config XTAL_FREQ_26
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depends on SOC_XTAL_SUPPORT_26M
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bool "26 MHz"
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config XTAL_FREQ_32
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depends on SOC_XTAL_SUPPORT_32M
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bool "32 MHz"
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config XTAL_FREQ_40
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depends on SOC_XTAL_SUPPORT_40M
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bool "40 MHz"
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config XTAL_FREQ_AUTO
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depends on SOC_XTAL_SUPPORT_AUTO_DETECT
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bool "Autodetect"
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endchoice
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# rtc_xtal_freq_t enum in soc/rtc.h lists the XTAL frequencies can be supported
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# SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported
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config XTAL_FREQ
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int
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default 24 if XTAL_FREQ_24
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default 26 if XTAL_FREQ_26
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default 32 if XTAL_FREQ_32
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default 40 if XTAL_FREQ_40
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default 0 if XTAL_FREQ_AUTO
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endmenu
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menu "Crypto DPA Protection"
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depends on SOC_CRYPTO_DPA_PROTECTION_SUPPORTED
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config ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP
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bool "Enable crypto DPA protection at startup"
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default y
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help
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This config controls the DPA (Differential Power Analysis) protection
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knob for the crypto peripherals. DPA protection dynamically adjusts the
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clock frequency of the crypto peripheral. DPA protection helps to make it
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difficult to perform SCA attacks on the crypto peripherals. However,
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there is also associated performance impact based on the security level
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set. Please refer to the TRM for more details.
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choice ESP_CRYPTO_DPA_PROTECTION_LEVEL
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prompt "DPA protection level"
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depends on ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP
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default ESP_CRYPTO_DPA_PROTECTION_LEVEL_LOW
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help
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Configure the DPA protection security level
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config ESP_CRYPTO_DPA_PROTECTION_LEVEL_LOW
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bool "Security level low"
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config ESP_CRYPTO_DPA_PROTECTION_LEVEL_MEDIUM
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bool "Security level medium"
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config ESP_CRYPTO_DPA_PROTECTION_LEVEL_HIGH
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bool "Security level high"
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endchoice
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config ESP_CRYPTO_DPA_PROTECTION_LEVEL
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int
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default 1 if ESP_CRYPTO_DPA_PROTECTION_LEVEL_LOW
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default 2 if ESP_CRYPTO_DPA_PROTECTION_LEVEL_MEDIUM
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default 3 if ESP_CRYPTO_DPA_PROTECTION_LEVEL_HIGH
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endmenu
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# Invisible bringup bypass options for esp_hw_support component
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config ESP_BRINGUP_BYPASS_CPU_CLK_SETTING
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bool
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default y if !SOC_CLK_TREE_SUPPORTED
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default n
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help
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This option is only used for new chip bringup, when
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clock support isn't done yet. So with this option,
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we use xtal on FPGA as the clock source.
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endmenu
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