mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
20b7f0ec87
1. fix infinite loop problem when init phy device 2. fix infinite loop problem when reset mac 3. fix little bugs in ethernetif_init 4. fix incompatible return value between lwip and esp-idf Closes https://github.com/espressif/esp-idf/issues/2331 Closes https://github.com/espressif/esp-idf/issues/2141
180 lines
6.8 KiB
C
180 lines
6.8 KiB
C
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_eth.h"
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#include "eth_phy/phy_tlk110.h"
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#include "eth_phy/phy_reg.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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/* Value of MII_PHY_IDENTIFIER_REG for TI TLK110,
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Excluding bottom 4 bytes of ID2, used for model revision
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*/
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#define TLK110_PHY_ID1 0x2000
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#define TLK110_PHY_ID2 0xa210
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#define TLK110_PHY_ID2_MASK 0xFFF0
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/* TLK110-specific registers */
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#define SW_STRAP_CONTROL_REG (0x9)
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#define SW_STRAP_CONFIG_DONE BIT(15)
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#define AUTO_MDIX_ENABLE BIT(14)
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#define AUTO_NEGOTIATION_ENABLE BIT(13)
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#define AN_1 BIT(12)
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#define AN_0 BIT(11)
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#define LED_CFG BIT(10)
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#define RMII_ENHANCED_MODE BIT(9)
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#define DEFAULT_STRAP_CONFIG (AUTO_MDIX_ENABLE|AUTO_NEGOTIATION_ENABLE|AN_1|AN_0|LED_CFG)
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#define PHY_STATUS_REG (0x10)
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#define AUTO_NEGOTIATION_STATUS BIT(4)
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#define DUPLEX_STATUS BIT(2)
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#define SPEED_STATUS BIT(1)
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#define CABLE_DIAGNOSTIC_CONTROL_REG (0x1e)
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#define DIAGNOSTIC_DONE BIT(1)
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#define PHY_RESET_CONTROL_REG (0x1f)
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#define SOFTWARE_RESET BIT(15)
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static const char *TAG = "tlk110";
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void phy_tlk110_check_phy_init(void)
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{
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phy_tlk110_dump_registers();
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esp_eth_smi_wait_set(MII_BASIC_MODE_STATUS_REG, MII_AUTO_NEGOTIATION_COMPLETE, 0);
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esp_eth_smi_wait_set(PHY_STATUS_REG, AUTO_NEGOTIATION_STATUS, 0);
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esp_eth_smi_wait_set(CABLE_DIAGNOSTIC_CONTROL_REG, DIAGNOSTIC_DONE, 0);
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}
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eth_speed_mode_t phy_tlk110_get_speed_mode(void)
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{
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if ((esp_eth_smi_read(PHY_STATUS_REG) & SPEED_STATUS ) != SPEED_STATUS) {
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ESP_LOGD(TAG, "phy_tlk110_get_speed_mode(100)");
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return ETH_SPEED_MODE_100M;
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} else {
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ESP_LOGD(TAG, "phy_tlk110_get_speed_mode(10)");
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return ETH_SPEED_MODE_10M;
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}
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}
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eth_duplex_mode_t phy_tlk110_get_duplex_mode(void)
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{
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if ((esp_eth_smi_read(PHY_STATUS_REG) & DUPLEX_STATUS ) == DUPLEX_STATUS) {
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ESP_LOGD(TAG, "phy_tlk110_get_duplex_mode(FULL)");
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return ETH_MODE_FULLDUPLEX;
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} else {
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ESP_LOGD(TAG, "phy_tlk110_get_duplex_mode(HALF)");
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return ETH_MODE_HALFDUPLEX;
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}
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}
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void phy_tlk110_power_enable(bool enable)
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{
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if (enable) {
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esp_eth_smi_write(SW_STRAP_CONTROL_REG, DEFAULT_STRAP_CONFIG | SW_STRAP_CONFIG_DONE);
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// TODO: only do this if config.flow_ctrl_enable == true
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phy_mii_enable_flow_ctrl();
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}
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}
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esp_err_t phy_tlk110_init(void)
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{
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ESP_LOGD(TAG, "phy_tlk110_init()");
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phy_tlk110_dump_registers();
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esp_eth_smi_write(PHY_RESET_CONTROL_REG, SOFTWARE_RESET);
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esp_err_t res1, res2;
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// Call esp_eth_smi_wait_value() with a timeout so it prints an error periodically
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res1 = esp_eth_smi_wait_value(MII_PHY_IDENTIFIER_1_REG, TLK110_PHY_ID1, UINT16_MAX, 1000);
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res2 = esp_eth_smi_wait_value(MII_PHY_IDENTIFIER_2_REG, TLK110_PHY_ID2, TLK110_PHY_ID2_MASK, 1000);
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esp_eth_smi_write(SW_STRAP_CONTROL_REG,
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DEFAULT_STRAP_CONFIG | SW_STRAP_CONFIG_DONE);
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ets_delay_us(300);
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// TODO: only do this if config.flow_ctrl_enable == true
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phy_mii_enable_flow_ctrl();
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if (res1 == ESP_OK && res2 == ESP_OK) {
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return ESP_OK;
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} else {
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return ESP_ERR_TIMEOUT;
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}
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}
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const eth_config_t phy_tlk110_default_ethernet_config = {
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// PHY address configured by PHYADx pins. Default value of 0x1
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// is used if all pins are unconnected.
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.phy_addr = 0x1,
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.mac_mode = ETH_MODE_RMII,
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.clock_mode = ETH_CLOCK_GPIO0_IN,
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//Only FULLDUPLEX mode support flow ctrl now!
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.flow_ctrl_enable = true,
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.phy_init = phy_tlk110_init,
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.phy_check_init = phy_tlk110_check_phy_init,
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.phy_check_link = phy_mii_check_link_status,
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.phy_get_speed_mode = phy_tlk110_get_speed_mode,
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.phy_get_duplex_mode = phy_tlk110_get_duplex_mode,
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.phy_get_partner_pause_enable = phy_mii_get_partner_pause_enable,
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.phy_power_enable = phy_tlk110_power_enable,
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.reset_timeout_ms = 1000
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};
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void phy_tlk110_dump_registers()
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{
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ESP_LOGD(TAG, "TLK110 Registers:");
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ESP_LOGD(TAG, "BMCR 0x%04x", esp_eth_smi_read(0x0));
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ESP_LOGD(TAG, "BMSR 0x%04x", esp_eth_smi_read(0x1));
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ESP_LOGD(TAG, "PHYIDR1 0x%04x", esp_eth_smi_read(0x2));
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ESP_LOGD(TAG, "PHYIDR2 0x%04x", esp_eth_smi_read(0x3));
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ESP_LOGD(TAG, "ANAR 0x%04x", esp_eth_smi_read(0x4));
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ESP_LOGD(TAG, "ANLPAR 0x%04x", esp_eth_smi_read(0x5));
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ESP_LOGD(TAG, "ANER 0x%04x", esp_eth_smi_read(0x6));
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ESP_LOGD(TAG, "ANNPTR 0x%04x", esp_eth_smi_read(0x7));
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ESP_LOGD(TAG, "ANLNPTR 0x%04x", esp_eth_smi_read(0x8));
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ESP_LOGD(TAG, "SWSCR1 0x%04x", esp_eth_smi_read(0x9));
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ESP_LOGD(TAG, "SWSCR2 0x%04x", esp_eth_smi_read(0xa));
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ESP_LOGD(TAG, "SWSCR3 0x%04x", esp_eth_smi_read(0xb));
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ESP_LOGD(TAG, "REGCR 0x%04x", esp_eth_smi_read(0xd));
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ESP_LOGD(TAG, "ADDAR 0x%04x", esp_eth_smi_read(0xe));
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ESP_LOGD(TAG, "PHYSTS 0x%04x", esp_eth_smi_read(0x10));
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ESP_LOGD(TAG, "PHYSCR 0x%04x", esp_eth_smi_read(0x11));
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ESP_LOGD(TAG, "MISR1 0x%04x", esp_eth_smi_read(0x12));
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ESP_LOGD(TAG, "MISR2 0x%04x", esp_eth_smi_read(0x13));
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ESP_LOGD(TAG, "FCSCR 0x%04x", esp_eth_smi_read(0x14));
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ESP_LOGD(TAG, "RECR 0x%04x", esp_eth_smi_read(0x15));
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ESP_LOGD(TAG, "BISCR 0x%04x", esp_eth_smi_read(0x16));
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ESP_LOGD(TAG, "RBR 0x%04x", esp_eth_smi_read(0x17));
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ESP_LOGD(TAG, "LEDCR 0x%04x", esp_eth_smi_read(0x18));
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ESP_LOGD(TAG, "PHYCR 0x%04x", esp_eth_smi_read(0x19));
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ESP_LOGD(TAG, "10BTSCR 0x%04x", esp_eth_smi_read(0x1a));
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ESP_LOGD(TAG, "BICSR1 0x%04x", esp_eth_smi_read(0x1b));
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ESP_LOGD(TAG, "BICSR2 0x%04x", esp_eth_smi_read(0x1c));
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ESP_LOGD(TAG, "CDCR 0x%04x", esp_eth_smi_read(0x1e));
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ESP_LOGD(TAG, "TRXCPSR 0x%04x", esp_eth_smi_read(0x42));
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ESP_LOGD(TAG, "PWRBOCR 0x%04x", esp_eth_smi_read(0xae));
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ESP_LOGD(TAG, "VRCR 0x%04x", esp_eth_smi_read(0xD0));
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ESP_LOGD(TAG, "ALCDRR1 0x%04x", esp_eth_smi_read(0x155));
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ESP_LOGD(TAG, "CDSCR1 0x%04x", esp_eth_smi_read(0x170));
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ESP_LOGD(TAG, "CDSCR2 0x%04x", esp_eth_smi_read(0x171));
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}
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