mirror of
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394 lines
18 KiB
C
394 lines
18 KiB
C
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Soc capabilities file, describing the following chip attributes:
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* - Peripheral or feature supported or not
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* - Number of resources (peripheral, channel, etc.)
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* - Maximum / Minimum value of HW, including: buffer/fifo size, length of transaction, frequency
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* supported, etc.
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*
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* For boolean definitions:
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* - if true: `#define MODULE_[SUBMODULE_]SUPPORT_FEATURE 1`.
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* (`#define` blank string causes error when checking by `#if x`)
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* - if false: not define anything at all.
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* (`#ifdef x` is true even when `#define 0` is defined before.)
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*
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* The code depending on this file uses these boolean definitions as `#if x` or `#if !x`.
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* (`#ifdef/ifndef x` is not compatible with `#define x 0`. Though we don't suggest to use `#define
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* x 0`, it's still a risk.)
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*
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* ECO & exceptions:
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* For ECO-ed booleans, `#define x "Not determined"` for them. This will cause error when used by
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* `#if x` and `#if !x`, making these missing definitions more obvious.
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*
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* These defines are parsed and imported as kconfig variables via the script
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* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
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*
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* If this file is changed the script will automatically run the script
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* and generate the kconfig variables as part of the pre-commit hooks.
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*
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* It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32/include/soc/'`
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*
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* For more information see `tools/gen_soc_caps_kconfig/README.md`
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*/
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#pragma once
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#ifdef __has_include
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# if __has_include("sdkconfig.h")
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# include "sdkconfig.h"
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# define SOC_CAPS_ECO_VER CONFIG_ESP32_REV_MIN_FULL
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# endif
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#endif
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#if __DOXYGEN__ && !defined(SOC_CAPS_ECO_VER)
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#define SOC_CAPS_ECO_VER SOC_CAPS_ECO_VER_MAX
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#endif
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#ifndef SOC_CAPS_ECO_VER
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#warning ECO version not determined. Some ECO related caps will not be available.
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#warning Define SOC_CAPS_ECO_VER before including this header.
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// Define warning strings here for ECO-ed features to show error when they are used without being
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// defined correctly
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#define SOC_BROWNOUT_RESET_SUPPORTED "Not determined"
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#define SOC_TWAI_BRP_DIV_SUPPORTED "Not determined"
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#define SOC_DPORT_WORKAROUND "Not determined"
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#endif
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/*-------------------------- COMMON CAPS ---------------------------------------*/
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#define SOC_CAPS_ECO_VER_MAX 301
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#define SOC_ADC_SUPPORTED 1
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#define SOC_DAC_SUPPORTED 1
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#define SOC_MCPWM_SUPPORTED 1
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#define SOC_SDMMC_HOST_SUPPORTED 1
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#define SOC_BT_SUPPORTED 1
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#define SOC_PCNT_SUPPORTED 1
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#define SOC_WIFI_SUPPORTED 1
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#define SOC_SDIO_SLAVE_SUPPORTED 1
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#define SOC_TWAI_SUPPORTED 1
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#define SOC_EMAC_SUPPORTED 1
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#define SOC_ULP_SUPPORTED 1
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#define SOC_CCOMP_TIMER_SUPPORTED 1
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#define SOC_RTC_FAST_MEM_SUPPORTED 1
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#define SOC_RTC_SLOW_MEM_SUPPORTED 1
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#define SOC_RTC_MEM_SUPPORTED 1
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#define SOC_I2S_SUPPORTED 1
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#define SOC_RMT_SUPPORTED 1
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#define SOC_SDM_SUPPORTED 1
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#define SOC_LEDC_SUPPORTED 1
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#define SOC_I2C_SUPPORTED 1
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#define SOC_SUPPORT_COEXISTENCE 1
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#define SOC_AES_SUPPORTED 1
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#define SOC_MPI_SUPPORTED 1
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#define SOC_SHA_SUPPORTED 1
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#define SOC_FLASH_ENC_SUPPORTED 1
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#define SOC_SECURE_BOOT_SUPPORTED 1
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#define SOC_TOUCH_SENSOR_SUPPORTED 1
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#if SOC_CAPS_ECO_VER < 200
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#define SOC_DPORT_WORKAROUND 1
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#endif // SOC_CAPS_ECO_VER < 200
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#define SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL (5U)
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/*-------------------------- XTAL CAPS ---------------------------------------*/
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#define SOC_XTAL_SUPPORT_26M 1
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#define SOC_XTAL_SUPPORT_40M 1
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#define SOC_XTAL_SUPPORT_AUTO_DETECT 1
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/*-------------------------- ADC CAPS ----------------------------------------*/
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/*!< SAR ADC Module*/
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#define SOC_ADC_RTC_CTRL_SUPPORTED 1
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#define SOC_ADC_DIG_CTRL_SUPPORTED 1
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#define SOC_ADC_DMA_SUPPORTED 1
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#define SOC_ADC_PERIPH_NUM (2)
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#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 8: 10)
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#define SOC_ADC_MAX_CHANNEL_NUM (10)
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#define SOC_ADC_ATTEN_NUM (4)
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/*!< Digital */
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#define SOC_ADC_DIGI_CONTROLLER_NUM (2)
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#define SOC_ADC_PATT_LEN_MAX (16) //Two pattern table, each contains 16 items. Each item takes 1 byte. But only support ADC1 using DMA mode
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#define SOC_ADC_DIGI_MIN_BITWIDTH (9)
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#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
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#define SOC_ADC_DIGI_RESULT_BYTES (2)
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#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
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#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH (2*1000*1000)
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#define SOC_ADC_SAMPLE_FREQ_THRES_LOW (20*1000)
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/*!< RTC */
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#define SOC_ADC_RTC_MIN_BITWIDTH (9)
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#define SOC_ADC_RTC_MAX_BITWIDTH (12)
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/*-------------------------- BROWNOUT CAPS -----------------------------------*/
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#if SOC_CAPS_ECO_VER >= 100
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#define SOC_BROWNOUT_RESET_SUPPORTED 1
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#endif
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/*-------------------------- CACHE/MMU CAPS ----------------------------------*/
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#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
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#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM 5
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/*-------------------------- CPU CAPS ----------------------------------------*/
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#define SOC_CPU_CORES_NUM 2
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#define SOC_CPU_INTR_NUM 32
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#define SOC_CPU_HAS_FPU 1
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#define SOC_CPU_BREAKPOINTS_NUM 2
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#define SOC_CPU_WATCHPOINTS_NUM 2
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#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes
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/*-------------------------- DAC CAPS ----------------------------------------*/
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#define SOC_DAC_CHAN_NUM 2
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#define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit
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#define SOC_DAC_DMA_16BIT_ALIGN 1 // The DMA data should left shift 8 bit to be aligned with 16 bit
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/*-------------------------- GPIO CAPS ---------------------------------------*/
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// ESP32 has 1 GPIO peripheral
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#define SOC_GPIO_PORT (1U)
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#define SOC_GPIO_PIN_COUNT 40
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// SOC_GPIO_SUPPORT_RTC_INDEPENDENT not defined. On ESP32 those PADs which have RTC functions must
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// set pullup/down/capability via RTC register. On ESP32-S2, Digital IOs have their own registers to
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// control pullup/down/capability, independent with RTC registers.
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// 0~39 except from 24, 28~31 are valid
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#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT24 | BIT28 | BIT29 | BIT30 | BIT31))
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// GPIO >= 34 are input only
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#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39))
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// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM: 1, 3, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 21, 22, 23)
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#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0xEF0FEAULL
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// Support to configure slept status
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#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
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/*-------------------------- I2C CAPS ----------------------------------------*/
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// ESP32 has 2 I2C
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#define SOC_I2C_NUM (2)
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#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
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#define SOC_I2C_SUPPORT_SLAVE (1)
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#define SOC_I2C_SUPPORT_APB (1)
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/*-------------------------- I2S CAPS ----------------------------------------*/
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// ESP32 has 2 I2S
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#define SOC_I2S_NUM (2U)
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#define SOC_I2S_HW_VERSION_1 (1)
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#define SOC_I2S_SUPPORTS_APLL (1)
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#define SOC_I2S_SUPPORTS_PDM (1)
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#define SOC_I2S_SUPPORTS_PDM_TX (1)
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#define SOC_I2S_SUPPORTS_PDM_RX (1)
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#define SOC_I2S_SUPPORTS_ADC_DAC (1)
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#define SOC_I2S_SUPPORTS_ADC (1)
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#define SOC_I2S_SUPPORTS_DAC (1)
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#define SOC_I2S_SUPPORTS_LCD_CAMERA (1)
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#define SOC_I2S_TRANS_SIZE_ALIGN_WORD (1) // I2S DMA transfer size must be aligned to word
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#define SOC_I2S_LCD_I80_VARIANT (1) // I2S has a special LCD mode that can generate Intel 8080 TX timing
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/*-------------------------- LCD CAPS ----------------------------------------*/
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/* Notes: On esp32, LCD intel 8080 timing is generated by I2S peripheral */
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#define SOC_LCD_I80_SUPPORTED (1) /*!< Intel 8080 LCD is supported */
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#define SOC_LCD_I80_BUSES (2) /*!< Both I2S0/1 have LCD mode */
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#define SOC_LCD_I80_BUS_WIDTH (24) /*!< Intel 8080 bus width */
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/*-------------------------- LEDC CAPS ---------------------------------------*/
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#define SOC_LEDC_HAS_TIMER_SPECIFIC_MUX (1)
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#define SOC_LEDC_SUPPORT_APB_CLOCK (1)
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#define SOC_LEDC_SUPPORT_REF_TICK (1)
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#define SOC_LEDC_SUPPORT_HS_MODE (1)
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#define SOC_LEDC_CHANNEL_NUM (8)
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#define SOC_LEDC_TIMER_BIT_WIDE_NUM (20)
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/*-------------------------- MCPWM CAPS --------------------------------------*/
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#define SOC_MCPWM_GROUPS (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
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#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
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#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
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#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
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#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
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#define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
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#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of GPIO fault signals that each group has
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#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
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#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
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#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
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#define SOC_MCPWM_CLK_SUPPORT_PLL160M (1) ///< Support PLL160M as clock source
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/*-------------------------- MPU CAPS ----------------------------------------*/
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//TODO: correct the caller and remove unsupported lines
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#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
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#define SOC_MPU_MIN_REGION_SIZE 0x20000000U
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#define SOC_MPU_REGIONS_MAX_NUM 8
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#define SOC_MPU_REGION_RO_SUPPORTED 0
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#define SOC_MPU_REGION_WO_SUPPORTED 0
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/*-------------------------- PCNT CAPS ---------------------------------------*/
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#define SOC_PCNT_GROUPS (1U)
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#define SOC_PCNT_UNITS_PER_GROUP (8)
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#define SOC_PCNT_CHANNELS_PER_UNIT (2)
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#define SOC_PCNT_THRES_POINT_PER_UNIT (2)
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/*-------------------------- RMT CAPS ----------------------------------------*/
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#define SOC_RMT_GROUPS 1U /*!< One RMT group */
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#define SOC_RMT_TX_CANDIDATES_PER_GROUP 8 /*!< Number of channels that capable of Transmit in each group */
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#define SOC_RMT_RX_CANDIDATES_PER_GROUP 8 /*!< Number of channels that capable of Receive in each group */
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#define SOC_RMT_CHANNELS_PER_GROUP 8 /*!< Total 8 channels */
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#define SOC_RMT_MEM_WORDS_PER_CHANNEL 64 /*!< Each channel owns 64 words memory */
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#define SOC_RMT_SUPPORT_REF_TICK 1 /*!< Support set REF_TICK as the RMT clock source */
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#define SOC_RMT_SUPPORT_APB 1 /*!< Support set APB as the RMT clock source */
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#define SOC_RMT_CHANNEL_CLK_INDEPENDENT 1 /*!< Can select different source clock for each channel */
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/*-------------------------- RTCIO CAPS --------------------------------------*/
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#define SOC_RTCIO_PIN_COUNT 18
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#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
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#define SOC_RTCIO_HOLD_SUPPORTED 1
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#define SOC_RTCIO_WAKE_SUPPORTED 1
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/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
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#define SOC_SDM_GROUPS 1U
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#define SOC_SDM_CHANNELS_PER_GROUP 8
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/*-------------------------- SPI CAPS ----------------------------------------*/
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#define SOC_SPI_HD_BOTH_INOUT_SUPPORTED 1 //Support enabling MOSI and MISO phases together under Halfduplex mode
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#define SOC_SPI_AS_CS_SUPPORTED 1 //Support to toggle the CS while the clock toggles
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#define SOC_SPI_PERIPH_NUM 3
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#define SOC_SPI_DMA_CHAN_NUM 2
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#define SOC_SPI_PERIPH_CS_NUM(i) 3
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#define SOC_SPI_MAX_CS_NUM 3
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#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
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#define SOC_SPI_MAX_PRE_DIVIDER 8192
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// Although ESP32 doesn't has memspi, but keep consistent with following chips.(This means SPI0/1)
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#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
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// Peripheral supports DIO, DOUT, QIO, or QOUT
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#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host) ({(void)spi_host; 1;})
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/*-------------------------- TIMER GROUP CAPS --------------------------------*/
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#define SOC_TIMER_GROUPS (2)
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#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2)
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#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (64)
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#define SOC_TIMER_GROUP_TOTAL_TIMERS (4)
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#define SOC_TIMER_GROUP_SUPPORT_APB (1)
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/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
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#define SOC_TOUCH_VERSION_1 (1) /*!<Hardware version of touch sensor */
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#define SOC_TOUCH_SENSOR_NUM (10)
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#define SOC_TOUCH_PAD_MEASURE_WAIT_MAX (0xFF) /*!<The timer frequency is 8Mhz, the max value is 0xff */
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#define SOC_TOUCH_PAD_THRESHOLD_MAX (0) /*!<If set touch threshold max value, The touch sensor can't be in touched status */
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/*-------------------------- TWAI CAPS ---------------------------------------*/
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#define SOC_TWAI_BRP_MIN 2
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#if SOC_CAPS_ECO_VER >= 200
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# define SOC_TWAI_BRP_MAX 256
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# define SOC_TWAI_BRP_DIV_SUPPORTED 1
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# define SOC_TWAI_BRP_DIV_THRESH 128
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#else
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# define SOC_TWAI_BRP_MAX 128
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#endif
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#define SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT 1
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/*-------------------------- UART CAPS ---------------------------------------*/
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// ESP32 have 3 UART.
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#define SOC_UART_NUM (3)
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#define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */
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#define SOC_UART_SUPPORT_REF_TICK (1) /*!< Support REF_TICK as the clock source */
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#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
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#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
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/*-------------------------- SPIRAM CAPS -------------------------------------*/
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#define SOC_SPIRAM_SUPPORTED 1
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/*-------------------------- SPI MEM CAPS ---------------------------------------*/
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#define SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE (1)
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/*--------------------------- SHA CAPS ---------------------------------------*/
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/* ESP32 style SHA engine, where multiple states can be stored in parallel */
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#define SOC_SHA_SUPPORT_PARALLEL_ENG (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA384 (1)
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#define SOC_SHA_SUPPORT_SHA512 (1)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (4096)
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/*-------------------------- AES CAPS -----------------------------------------*/
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#define SOC_AES_SUPPORT_AES_128 (1)
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#define SOC_AES_SUPPORT_AES_192 (1)
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#define SOC_AES_SUPPORT_AES_256 (1)
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/*-------------------------- Secure Boot CAPS----------------------------*/
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/*
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* ESP32 ECO3 revision also supports `SOC_SECURE_BOOT_V2_RSA` but for that we will need selected ECO
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* version from `Kconfig`, which is not possible while generating `Kconfig.soc_caps.in` from this header.
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* Hence, for now we are handling this special capability in bootloader "security" configuration itself.
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*/
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#define SOC_SECURE_BOOT_V1 1
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#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 1
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/*-------------------------- Flash Encryption CAPS----------------------------*/
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#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32)
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/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
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#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
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/*-------------------------- Power Management CAPS ---------------------------*/
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#define SOC_PM_SUPPORT_EXT_WAKEUP (1)
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#define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*!<Supports waking up from touch pad trigger */
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#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
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#define SOC_PM_SUPPORT_RTC_FAST_MEM_PD (1)
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#define SOC_PM_SUPPORT_RTC_SLOW_MEM_PD (1)
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/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
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#define SOC_CLK_APLL_SUPPORTED (1)
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// apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)
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#define SOC_APLL_MULTIPLIER_OUT_MIN_HZ (350000000) // 350 MHz
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#define SOC_APLL_MULTIPLIER_OUT_MAX_HZ (500000000) // 500 MHz
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#define SOC_APLL_MIN_HZ (5303031) // 5.303031 MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
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#define SOC_APLL_MAX_HZ (125000000) // 125MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
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#define SOC_CLK_RC_FAST_D256_SUPPORTED (1)
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#define SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256 (1)
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/*-------------------------- SDMMC CAPS -----------------------------------------*/
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/* On ESP32, clock/cmd/data pins use IO MUX.
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* Card detect, write protect, interrupt use GPIO Matrix on all chips.
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*/
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#define SOC_SDMMC_USE_IOMUX 1
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#define SOC_SDMMC_NUM_SLOTS 2
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/*-------------------------- WI-FI HARDWARE CAPS -------------------------------*/
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#define SOC_WIFI_FTM_SUPPORT (0) /*!< FTM is not supported */
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#define SOC_WIFI_GCMP_SUPPORT (0) /*!< GCMP is not supported(GCMP128 and GCMP256) */
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#define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */
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#define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */
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#define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */
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/*---------------------------------- Bluetooth CAPS ----------------------------------*/
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#define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */
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#define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */
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#define SOC_BT_CLASSIC_SUPPORTED (1) /*!< Support Bluetooth Classic hardware */
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