mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
874a720286
update all struct headers to be more "standardized":
- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199
added helper macros to force peripheral registers being accessed in 32 bitwidth
added a check script into ci
335 lines
8.9 KiB
C
335 lines
8.9 KiB
C
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** SYSTEM TIMER REGISTER */
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/** Type of conf register
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* Configure system timer clock
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*/
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typedef union {
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struct {
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/** clk_fo : R/W; bitpos: [0]; default: 0;
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* system timer force clock enable
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*/
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uint32_t clk_fo: 1;
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uint32_t reserved_1: 30;
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/** clk_en : R/W; bitpos: [31]; default: 0;
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* register clock enable
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*/
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uint32_t clk_en: 1;
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};
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uint32_t val;
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} systimer_conf_reg_t;
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/** Type of load register
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* load value to system timer
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*/
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typedef union {
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struct {
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uint32_t reserved_0: 31;
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/** timer_load : WO; bitpos: [31]; default: 0;
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* load value to system timer
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*/
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uint32_t timer_load: 1;
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};
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uint32_t val;
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} systimer_load_reg_t;
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/** Type of load_hi register
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* High 32-bit load to system timer
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*/
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typedef union {
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struct {
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/** timer_load_hi : R/W; bitpos: [31:0]; default: 0;
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* High 32-bit load to system timer
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*/
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uint32_t timer_load_hi: 32;
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};
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uint32_t val;
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} systimer_load_hi_reg_t;
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/** Type of load_lo register
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* Low 32-bit load to system timer
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*/
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typedef union {
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struct {
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/** timer_load_lo : R/W; bitpos: [31:0]; default: 0;
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* Low 32-bit load to system timer
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*/
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uint32_t timer_load_lo: 32;
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};
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uint32_t val;
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} systimer_load_lo_reg_t;
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/** Type of step register
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* system timer accumulation step
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*/
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typedef union {
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struct {
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/** timer_xtal_step : R/W; bitpos: [9:0]; default: 80;
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* system timer accumulation step when using XTAL
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*/
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uint32_t timer_xtal_step: 10;
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/** timer_pll_step : R/W; bitpos: [19:10]; default: 1;
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* system timer accumulation step when using PLL
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*/
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uint32_t timer_pll_step: 10;
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} systimer_step_reg_t;
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/** Type of target_val register
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* System timer target value
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*/
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typedef struct {
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union {
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struct {
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/** timer_target_hi : R/W; bitpos: [31:0]; default: 0;
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* System timer target0 high 32-bit
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*/
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uint32_t timer_target_hi: 32;
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};
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uint32_t val;
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} hi;
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union {
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struct {
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/** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
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* System timer target0 low 32-bit
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*/
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uint32_t timer_target_lo: 32;
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};
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uint32_t val;
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} lo;
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} systimer_target_val_reg_t;
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/** Type of target_conf register
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* Configure system timer target work mode
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*/
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typedef union {
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struct {
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/** target_period : R/W; bitpos: [29:0]; default: 0;
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* System timer target alarm period
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*/
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uint32_t target_period: 30;
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/** target_period_mode : R/W; bitpos: [30]; default: 0;
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* Whether system timer target work in period mode
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*/
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uint32_t target_period_mode: 1;
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/** target_work_en : R/W; bitpos: [31]; default: 0;
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* system timer target work enable
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*/
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uint32_t target_work_en: 1;
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};
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uint32_t val;
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} systimer_target_conf_reg_t;
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/** Type of update register
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* Read out system timer value
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*/
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typedef union {
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struct {
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uint32_t reserved_0: 30;
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/** timer_value_valid : RO; bitpos: [30]; default: 0;
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* If it is valid to read out timer value from register
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*/
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uint32_t timer_value_valid: 1;
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/** timer_update : WO; bitpos: [31]; default: 0;
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* Update system timer value to register
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*/
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uint32_t timer_update: 1;
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};
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uint32_t val;
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} systimer_update_reg_t;
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/** Type of value_hi register
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* system timer high 32-bit
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*/
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typedef union {
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struct {
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/** timer_value_hi : RO; bitpos: [31:0]; default: 0;
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* system timer high 32-bit
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*/
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uint32_t timer_value_hi: 32;
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};
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uint32_t val;
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} systimer_value_hi_reg_t;
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/** Type of value_lo register
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* system timer low 32-bit
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*/
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typedef union {
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struct {
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/** timer_value_lo : RO; bitpos: [31:0]; default: 0;
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* system timer low 32-bit
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*/
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uint32_t timer_value_lo: 32;
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};
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uint32_t val;
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} systimer_value_lo_reg_t;
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/** Type of int_ena register
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* system timer interrupt enable
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*/
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typedef union {
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struct {
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/** systimer_int0_ena : R/W; bitpos: [0]; default: 0;
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* system timer target0 interrupt enable
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*/
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uint32_t systimer_int0_ena: 1;
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/** systimer_int1_ena : R/W; bitpos: [1]; default: 0;
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* system timer target1 interrupt enable
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*/
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uint32_t systimer_int1_ena: 1;
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/** systimer_int2_ena : R/W; bitpos: [2]; default: 0;
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* system timer target2 interrupt enable
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*/
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uint32_t systimer_int2_ena: 1;
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uint32_t reserved3: 29;
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};
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uint32_t val;
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} systimer_int_ena_reg_t;
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/** Type of int_raw register
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* system timer interrupt raw
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*/
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typedef union {
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struct {
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/** systimer_int0_raw : RO; bitpos: [0]; default: 0;
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* system timer target0 interrupt raw
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*/
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uint32_t systimer_int0_raw: 1;
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/** systimer_int1_raw : RO; bitpos: [1]; default: 0;
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* system timer target1 interrupt raw
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*/
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uint32_t systimer_int1_raw: 1;
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/** systimer_int2_raw : RO; bitpos: [2]; default: 0;
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* system timer target2 interrupt raw
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*/
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uint32_t systimer_int2_raw: 1;
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uint32_t reserved3: 29;
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};
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uint32_t val;
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} systimer_int_raw_reg_t;
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/** Type of int_clr register
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* system timer interrupt clear
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*/
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typedef union {
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struct {
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/** systimer_int0_clr : WO; bitpos: [0]; default: 0;
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* system timer target0 interrupt clear
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*/
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uint32_t systimer_int0_clr: 1;
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/** systimer_int1_clr : WO; bitpos: [1]; default: 0;
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* system timer target1 interrupt clear
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*/
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uint32_t systimer_int1_clr: 1;
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/** systimer_int2_clr : WO; bitpos: [2]; default: 0;
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* system timer target2 interrupt clear
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*/
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uint32_t systimer_int2_clr: 1;
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uint32_t reserved3: 29;
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};
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uint32_t val;
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} systimer_int_clr_reg_t;
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/** DATE */
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/** Type of date register
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* system timer register version
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [31:0]; default: 25194848;
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* system timer register version
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*/
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uint32_t date: 32;
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};
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uint32_t val;
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} systimer_date_reg_t;
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typedef struct {
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volatile systimer_conf_reg_t conf;
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volatile systimer_load_reg_t load;
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volatile systimer_load_hi_reg_t load_hi;
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volatile systimer_load_lo_reg_t load_lo;
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volatile systimer_step_reg_t step;
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volatile systimer_target_val_reg_t target_val[3];
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volatile systimer_target_conf_reg_t target_conf[3];
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volatile systimer_update_reg_t update;
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volatile systimer_value_hi_reg_t value_hi;
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volatile systimer_value_lo_reg_t value_lo;
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volatile systimer_int_ena_reg_t int_ena;
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volatile systimer_int_raw_reg_t int_raw;
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volatile systimer_int_clr_reg_t int_clr;
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uint32_t reserved_050;
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uint32_t reserved_054;
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uint32_t reserved_058;
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uint32_t reserved_05c;
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uint32_t reserved_060;
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uint32_t reserved_064;
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uint32_t reserved_068;
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uint32_t reserved_06c;
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uint32_t reserved_070;
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uint32_t reserved_074;
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uint32_t reserved_078;
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uint32_t reserved_07c;
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uint32_t reserved_080;
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uint32_t reserved_084;
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uint32_t reserved_088;
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uint32_t reserved_08c;
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uint32_t reserved_090;
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uint32_t reserved_094;
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uint32_t reserved_098;
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uint32_t reserved_09c;
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uint32_t reserved_0a0;
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uint32_t reserved_0a4;
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uint32_t reserved_0a8;
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uint32_t reserved_0ac;
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uint32_t reserved_0b0;
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uint32_t reserved_0b4;
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uint32_t reserved_0b8;
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uint32_t reserved_0bc;
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uint32_t reserved_0c0;
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uint32_t reserved_0c4;
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uint32_t reserved_0c8;
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uint32_t reserved_0cc;
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uint32_t reserved_0d0;
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uint32_t reserved_0d4;
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uint32_t reserved_0d8;
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uint32_t reserved_0dc;
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uint32_t reserved_0e0;
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uint32_t reserved_0e4;
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uint32_t reserved_0e8;
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uint32_t reserved_0ec;
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uint32_t reserved_0f0;
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uint32_t reserved_0f4;
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uint32_t reserved_0f8;
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volatile systimer_date_reg_t date;
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} systimer_dev_t;
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extern systimer_dev_t SYSTIMER;
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#ifdef __cplusplus
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}
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#endif
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