mirror of
https://github.com/espressif/esp-idf.git
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114 lines
4.2 KiB
C
114 lines
4.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <esp_bit_defs.h>
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#include "esp_log.h"
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#include "esp_efuse.h"
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#include "esp_efuse_table.h"
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#include "esp_efuse_rtc_calib.h"
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#include "hal/adc_types.h"
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int esp_efuse_rtc_calib_get_ver(void)
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{
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uint32_t blk_ver_major = 0;
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esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366
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uint32_t cali_version = (blk_ver_major == 0) ? ESP_EFUSE_ADC_CALIB_VER : 0;
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if (!cali_version) {
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ESP_LOGW("eFuse", "calibration efuse version does not match, set default version to 0");
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}
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return cali_version;
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}
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uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten)
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{
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assert((version >= ESP_EFUSE_ADC_CALIB_VER_MIN) &&
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(version <= ESP_EFUSE_ADC_CALIB_VER_MAX));
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assert(atten <= ADC_ATTEN_DB_11);
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(void) adc_unit;
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if (atten == ADC_ATTEN_DB_2_5 || atten == ADC_ATTEN_DB_6) {
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/**
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* - ESP32C2 only supports HW calibration on ADC_ATTEN_DB_0 and ADC_ATTEN_DB_11
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* - For other attenuation, we just return default value, which is 0.
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*/
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return 0;
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}
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int32_t adc_icode_diff_atten0 = 0;
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int32_t adc_icode_diff_atten3 = 0;
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int efuse_icode_bits = 0;
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efuse_icode_bits = esp_efuse_get_field_size(ESP_EFUSE_ADC1_INIT_CODE_ATTEN0);
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ESP_ERROR_CHECK(esp_efuse_read_field_blob(ESP_EFUSE_ADC1_INIT_CODE_ATTEN0, &adc_icode_diff_atten0, efuse_icode_bits));
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adc_icode_diff_atten0 = ((adc_icode_diff_atten0 & BIT(7)) != 0) ? -(adc_icode_diff_atten0 & 0x7f): adc_icode_diff_atten0;
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efuse_icode_bits = esp_efuse_get_field_size(ESP_EFUSE_ADC1_INIT_CODE_ATTEN3);
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ESP_ERROR_CHECK(esp_efuse_read_field_blob(ESP_EFUSE_ADC1_INIT_CODE_ATTEN3, &adc_icode_diff_atten3, efuse_icode_bits));
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ESP_EARLY_LOGV("eFuse", "adc_icode_diff_atten0: 0d%"PRId32", adc_icode_diff_atten3: 0d%"PRId32, adc_icode_diff_atten0, adc_icode_diff_atten3);
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uint32_t init_code = 0;
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if (atten == ADC_ATTEN_DB_0) {
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init_code = adc_icode_diff_atten0 + 2160;
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} else {
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//ADC_ATTEN_DB_11
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init_code = adc_icode_diff_atten3 + adc_icode_diff_atten0 + 2160;
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}
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return init_code;
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}
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esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, int atten, uint32_t *out_digi, uint32_t *out_vol_mv)
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{
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assert((version >= ESP_EFUSE_ADC_CALIB_VER_MIN) &&
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(version <= ESP_EFUSE_ADC_CALIB_VER_MAX));
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assert(atten <= ADC_ATTEN_DB_11);
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(void) adc_unit;
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if (atten == ADC_ATTEN_DB_2_5 || atten == ADC_ATTEN_DB_6) {
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/**
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* - ESP32C2 only supports SW calibration on ADC_ATTEN_DB_0 and ADC_ATTEN_DB_11
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* - For other attenuation, we need to return an error, informing upper layer SW calibration driver
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* to deal with the error.
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*/
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return ESP_ERR_INVALID_ARG;
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}
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int32_t adc_vol_diff_atten0 = 0;
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int32_t adc_vol_diff_atten3 = 0;
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int efuse_vol_bits = 0;
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efuse_vol_bits = esp_efuse_get_field_size(ESP_EFUSE_ADC1_CAL_VOL_ATTEN0);
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ESP_ERROR_CHECK(esp_efuse_read_field_blob(ESP_EFUSE_ADC1_CAL_VOL_ATTEN0, &adc_vol_diff_atten0, efuse_vol_bits));
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adc_vol_diff_atten0 = ((adc_vol_diff_atten0 & BIT(7)) != 0) ? -(adc_vol_diff_atten0 & 0x7f): adc_vol_diff_atten0;
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efuse_vol_bits = esp_efuse_get_field_size(ESP_EFUSE_ADC1_CAL_VOL_ATTEN3);
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ESP_ERROR_CHECK(esp_efuse_read_field_blob(ESP_EFUSE_ADC1_CAL_VOL_ATTEN3, &adc_vol_diff_atten3, efuse_vol_bits));
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adc_vol_diff_atten3 = ((adc_vol_diff_atten3 & BIT(5)) != 0) ? -(adc_vol_diff_atten3 & 0x1f): adc_vol_diff_atten3;
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ESP_EARLY_LOGV("eFuse", "adc_vol_diff_atten0: 0d%"PRId32", adc_vol_diff_atten3: 0d%"PRId32, adc_vol_diff_atten0, adc_vol_diff_atten3);
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if (atten == ADC_ATTEN_DB_0) {
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*out_digi = adc_vol_diff_atten0 + 1540;
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*out_vol_mv = 400;
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} else {
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//ADC_ATTEN_DB_11
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*out_digi = adc_vol_diff_atten0 + 1540 - adc_vol_diff_atten3 - 123;
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*out_vol_mv = 1370;
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}
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return ESP_OK;
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}
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esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal)
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{
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// Currently calibration is not supported on ESP32-C2, IDF-5236
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*tsens_cal = 0.0;
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return ESP_OK;
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}
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