mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
129 lines
3.2 KiB
C
129 lines
3.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include <sys/param.h>
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#include "soc/soc_caps.h"
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#include "hal/efuse_ll.h"
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#include "hal/assert.h"
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#include "hal/efuse_hal.h"
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#include "soc/syscon_reg.h"
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#include "esp_attr.h"
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IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
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{
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uint8_t eco_bit0 = efuse_ll_get_chip_ver_rev1();
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uint8_t eco_bit1 = efuse_ll_get_chip_ver_rev2();
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uint8_t eco_bit2 = (REG_READ(SYSCON_DATE_REG) & 0x80000000) >> 31;
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uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
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uint32_t chip_ver = 0;
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switch (combine_value) {
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case 0:
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chip_ver = 0;
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break;
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case 1:
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chip_ver = 1;
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break;
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case 3:
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chip_ver = 2;
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break;
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#if CONFIG_IDF_ENV_FPGA
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case 4: /* Empty efuses, but SYSCON_DATE_REG bit is set */
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chip_ver = 3;
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break;
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#endif // CONFIG_IDF_ENV_FPGA
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case 7:
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chip_ver = 3;
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break;
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default:
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chip_ver = 0;
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break;
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}
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return chip_ver;
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}
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IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
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{
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return efuse_ll_get_chip_wafer_version_minor();
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}
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uint32_t efuse_hal_get_rated_freq_mhz(void)
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{
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//Check if ESP32 is rated for a CPU frequency of 160MHz only
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if (efuse_ll_get_chip_cpu_freq_rated() && efuse_ll_get_chip_cpu_freq_low()) {
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return 160;
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}
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return 240;
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}
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/******************* eFuse control functions *************************/
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void efuse_hal_set_timing(uint32_t apb_freq_mhz)
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{
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uint32_t clk_sel0;
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uint32_t clk_sel1;
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uint32_t dac_clk_div;
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if (apb_freq_mhz <= 26) {
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clk_sel0 = 250;
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clk_sel1 = 255;
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dac_clk_div = 52;
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} else if (apb_freq_mhz <= 40) {
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clk_sel0 = 160;
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clk_sel1 = 255;
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dac_clk_div = 80;
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} else {
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clk_sel0 = 80;
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clk_sel1 = 128;
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dac_clk_div = 100;
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}
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efuse_ll_set_dac_clk_div(dac_clk_div);
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efuse_ll_set_dac_clk_sel0(clk_sel0);
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efuse_ll_set_dac_clk_sel1(clk_sel1);
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}
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void efuse_hal_read(void)
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{
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efuse_ll_set_conf_read_op_code();
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efuse_ll_set_read_cmd();
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while (efuse_ll_get_cmd() != 0) { };
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}
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void efuse_hal_clear_program_registers(void)
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{
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for (uint32_t r = EFUSE_BLK0_WDATA0_REG; r <= EFUSE_BLK0_WDATA6_REG; r += 4) {
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REG_WRITE(r, 0);
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}
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for (uint32_t r = EFUSE_BLK1_WDATA0_REG; r <= EFUSE_BLK1_WDATA7_REG; r += 4) {
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REG_WRITE(r, 0);
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}
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for (uint32_t r = EFUSE_BLK2_WDATA0_REG; r <= EFUSE_BLK2_WDATA7_REG; r += 4) {
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REG_WRITE(r, 0);
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}
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for (uint32_t r = EFUSE_BLK3_WDATA0_REG; r <= EFUSE_BLK3_WDATA7_REG; r += 4) {
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REG_WRITE(r, 0);
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}
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}
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void efuse_hal_program(uint32_t block)
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{
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(void) block;
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// Permanently update values written to the efuse write registers
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efuse_ll_set_conf_write_op_code();
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efuse_ll_set_pgm_cmd();
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while (efuse_ll_get_cmd() != 0) { };
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efuse_hal_read();
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}
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/******************* eFuse control functions *************************/
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bool efuse_hal_is_coding_error_in_block(unsigned block)
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{
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return block > 0 &&
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efuse_ll_get_coding_scheme() == 1 && // 3/4 coding scheme
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efuse_ll_get_dec_warnings(block);
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}
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