mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
874a720286
update all struct headers to be more "standardized":
- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199
added helper macros to force peripheral registers being accessed in 32 bitwidth
added a check script into ci
433 lines
15 KiB
C
433 lines
15 KiB
C
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_APB_SARADC_STRUCT_H_
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#define _SOC_APB_SARADC_STRUCT_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct apb_saradc_dev_s {
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union {
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struct {
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uint32_t start_force: 1;
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uint32_t start: 1;
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uint32_t reserved2: 1;
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uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
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uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
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uint32_t sar_clk_gated: 1;
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uint32_t sar_clk_div: 8; /*SAR clock divider*/
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uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
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uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
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uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
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uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
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uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/
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uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
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uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/
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uint32_t reserved29: 1;
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uint32_t wait_arb_cycle: 2; /*wait arbit signal stable after sar_done*/
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};
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uint32_t val;
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} ctrl;
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union {
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struct {
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uint32_t meas_num_limit: 1;
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uint32_t max_meas_num: 8; /*max conversion number*/
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uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
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uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
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uint32_t timer_sel: 1; /*1: select saradc timer 0: i2s_ws trigger*/
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uint32_t timer_target: 12; /*to set saradc timer target*/
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uint32_t timer_en: 1; /*to enable saradc timer trigger*/
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uint32_t reserved25: 7;
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};
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uint32_t val;
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} ctrl2;
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union {
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struct {
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uint32_t reserved0: 16;
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uint32_t sample_num: 8; /*sample number*/
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uint32_t sample_cycle: 8; /*sample cycles*/
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};
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uint32_t val;
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} fsm;
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union {
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struct {
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uint32_t xpd_wait: 8;
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uint32_t rstb_wait: 8;
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uint32_t standby_wait: 8;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} fsm_wait;
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uint32_t sar1_status; /**/
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uint32_t sar2_status; /**/
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uint32_t sar1_patt_tab[4]; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
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uint32_t sar2_patt_tab[4];
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union {
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struct {
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uint32_t reserved0: 2;
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uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/
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uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/
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uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/
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uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/
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uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/
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uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/
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uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/
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uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/
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uint32_t reserved13: 19;
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};
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uint32_t val;
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} apb_adc_arb_ctrl;
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union {
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struct {
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uint32_t adc2_filter_reset: 1; /*reset_adc2_filter*/
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uint32_t adc1_filter_reset: 1; /*reset_adc1_filter*/
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uint32_t reserved2: 14;
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uint32_t adc2_filter_factor: 7; /*apb_adc2_filter_factor*/
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uint32_t adc1_filter_factor: 7; /*apb_adc1_filter_factor*/
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uint32_t adc2_filter_en: 1; /*enable apb_adc2_filter*/
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uint32_t adc1_filter_en: 1; /*enable apb_adc1_filter*/
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};
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uint32_t val;
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} filter_ctrl;
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union {
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struct {
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uint32_t adc2_filter_data:16;
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uint32_t adc1_filter_data:16;
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};
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uint32_t val;
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} filter_status;
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union {
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struct {
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uint32_t clk_en: 1;
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uint32_t reserved1: 1;
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uint32_t adc2_thres_mode: 1;
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uint32_t adc1_thres_mode: 1;
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uint32_t adc2_thres: 13;
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uint32_t adc1_thres: 13;
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uint32_t adc2_thres_en: 1;
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uint32_t adc1_thres_en: 1;
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};
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uint32_t val;
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} thres_ctrl;
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union {
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struct {
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uint32_t reserved0: 28;
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uint32_t adc2_thres: 1;
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uint32_t adc1_thres: 1;
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uint32_t adc2_done: 1;
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uint32_t adc1_done: 1;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t reserved0: 28;
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uint32_t adc2_thres: 1;
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uint32_t adc1_thres: 1;
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uint32_t adc2_done: 1;
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uint32_t adc1_done: 1;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t reserved0: 28;
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uint32_t adc2_thres: 1;
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uint32_t adc1_thres: 1;
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uint32_t adc2_done: 1;
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uint32_t adc1_done: 1;
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};
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uint32_t val;
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} int_st;
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union {
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struct {
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uint32_t reserved0: 28;
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uint32_t adc2_thres: 1;
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uint32_t adc1_thres: 1;
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uint32_t adc2_done: 1;
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uint32_t adc1_done: 1;
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t apb_adc_eof_num: 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
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uint32_t reserved16: 14;
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uint32_t apb_adc_reset_fsm: 1; /*reset_apb_adc_state*/
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uint32_t apb_adc_trans: 1; /*enable apb_adc use spi_dma*/
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};
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uint32_t val;
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} dma_conf;
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union {
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struct {
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uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/
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uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/
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uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/
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uint32_t reserved20: 1;
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uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/
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uint32_t reserved23: 9;
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};
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uint32_t val;
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} apb_adc_clkm_conf;
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union {
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struct {
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uint32_t dac_timer_target: 12; /*dac_timer target*/
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uint32_t dac_timer_en: 1; /*enable read dac data*/
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uint32_t apb_dac_alter_mode: 1; /*enable dac alter mode*/
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uint32_t apb_dac_trans: 1; /*enable dma_dac*/
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uint32_t dac_reset_fifo: 1;
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uint32_t apb_dac_rst: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} apb_dac_ctrl;
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uint32_t reserved_64;
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uint32_t reserved_68;
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uint32_t reserved_6c;
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uint32_t reserved_70;
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uint32_t reserved_74;
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uint32_t reserved_78;
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uint32_t reserved_7c;
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uint32_t reserved_80;
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uint32_t reserved_84;
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uint32_t reserved_88;
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uint32_t reserved_8c;
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uint32_t reserved_90;
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uint32_t reserved_94;
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uint32_t reserved_98;
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uint32_t reserved_9c;
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uint32_t reserved_a0;
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uint32_t reserved_a4;
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uint32_t reserved_a8;
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uint32_t reserved_ac;
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uint32_t reserved_b0;
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uint32_t reserved_b4;
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uint32_t reserved_b8;
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uint32_t reserved_bc;
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uint32_t reserved_c0;
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uint32_t reserved_c4;
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uint32_t reserved_c8;
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uint32_t reserved_cc;
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uint32_t reserved_d0;
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uint32_t reserved_d4;
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uint32_t reserved_d8;
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uint32_t reserved_dc;
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uint32_t reserved_e0;
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uint32_t reserved_e4;
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uint32_t reserved_e8;
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uint32_t reserved_ec;
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uint32_t reserved_f0;
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uint32_t reserved_f4;
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uint32_t reserved_f8;
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uint32_t reserved_fc;
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uint32_t reserved_100;
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uint32_t reserved_104;
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uint32_t reserved_108;
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uint32_t reserved_10c;
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uint32_t reserved_110;
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uint32_t reserved_114;
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uint32_t reserved_118;
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uint32_t reserved_11c;
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uint32_t reserved_120;
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uint32_t reserved_124;
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uint32_t reserved_128;
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uint32_t reserved_12c;
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uint32_t reserved_130;
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uint32_t reserved_134;
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uint32_t reserved_138;
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uint32_t reserved_13c;
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uint32_t reserved_140;
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uint32_t reserved_144;
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uint32_t reserved_148;
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uint32_t reserved_14c;
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uint32_t reserved_150;
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uint32_t reserved_154;
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uint32_t reserved_158;
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uint32_t reserved_15c;
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uint32_t reserved_160;
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uint32_t reserved_164;
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uint32_t reserved_168;
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uint32_t reserved_16c;
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uint32_t reserved_170;
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uint32_t reserved_174;
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uint32_t reserved_178;
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uint32_t reserved_17c;
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uint32_t reserved_180;
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uint32_t reserved_184;
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uint32_t reserved_188;
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uint32_t reserved_18c;
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uint32_t reserved_190;
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uint32_t reserved_194;
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uint32_t reserved_198;
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uint32_t reserved_19c;
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uint32_t reserved_1a0;
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uint32_t reserved_1a4;
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uint32_t reserved_1a8;
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uint32_t reserved_1ac;
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uint32_t reserved_1b0;
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uint32_t reserved_1b4;
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uint32_t reserved_1b8;
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uint32_t reserved_1bc;
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uint32_t reserved_1c0;
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uint32_t reserved_1c4;
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uint32_t reserved_1c8;
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uint32_t reserved_1cc;
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uint32_t reserved_1d0;
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uint32_t reserved_1d4;
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uint32_t reserved_1d8;
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uint32_t reserved_1dc;
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uint32_t reserved_1e0;
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uint32_t reserved_1e4;
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uint32_t reserved_1e8;
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uint32_t reserved_1ec;
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uint32_t reserved_1f0;
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uint32_t reserved_1f4;
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uint32_t reserved_1f8;
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uint32_t reserved_1fc;
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uint32_t reserved_200;
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uint32_t reserved_204;
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uint32_t reserved_208;
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uint32_t reserved_20c;
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uint32_t reserved_210;
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uint32_t reserved_214;
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uint32_t reserved_218;
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uint32_t reserved_21c;
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uint32_t reserved_220;
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uint32_t reserved_224;
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uint32_t reserved_228;
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uint32_t reserved_22c;
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uint32_t reserved_230;
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uint32_t reserved_234;
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uint32_t reserved_238;
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uint32_t reserved_23c;
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uint32_t reserved_240;
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uint32_t reserved_244;
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uint32_t reserved_248;
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uint32_t reserved_24c;
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uint32_t reserved_250;
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uint32_t reserved_254;
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uint32_t reserved_258;
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uint32_t reserved_25c;
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uint32_t reserved_260;
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uint32_t reserved_264;
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uint32_t reserved_268;
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uint32_t reserved_26c;
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uint32_t reserved_270;
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uint32_t reserved_274;
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uint32_t reserved_278;
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uint32_t reserved_27c;
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uint32_t reserved_280;
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uint32_t reserved_284;
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uint32_t reserved_288;
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uint32_t reserved_28c;
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uint32_t reserved_290;
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uint32_t reserved_294;
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uint32_t reserved_298;
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uint32_t reserved_29c;
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uint32_t reserved_2a0;
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uint32_t reserved_2a4;
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uint32_t reserved_2a8;
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uint32_t reserved_2ac;
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uint32_t reserved_2b0;
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uint32_t reserved_2b4;
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uint32_t reserved_2b8;
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uint32_t reserved_2bc;
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uint32_t reserved_2c0;
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uint32_t reserved_2c4;
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uint32_t reserved_2c8;
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uint32_t reserved_2cc;
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uint32_t reserved_2d0;
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uint32_t reserved_2d4;
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uint32_t reserved_2d8;
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uint32_t reserved_2dc;
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uint32_t reserved_2e0;
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uint32_t reserved_2e4;
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uint32_t reserved_2e8;
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uint32_t reserved_2ec;
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uint32_t reserved_2f0;
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uint32_t reserved_2f4;
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uint32_t reserved_2f8;
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uint32_t reserved_2fc;
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uint32_t reserved_300;
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uint32_t reserved_304;
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uint32_t reserved_308;
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uint32_t reserved_30c;
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uint32_t reserved_310;
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uint32_t reserved_314;
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uint32_t reserved_318;
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uint32_t reserved_31c;
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uint32_t reserved_320;
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uint32_t reserved_324;
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uint32_t reserved_328;
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uint32_t reserved_32c;
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uint32_t reserved_330;
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uint32_t reserved_334;
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uint32_t reserved_338;
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uint32_t reserved_33c;
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uint32_t reserved_340;
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uint32_t reserved_344;
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uint32_t reserved_348;
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uint32_t reserved_34c;
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uint32_t reserved_350;
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uint32_t reserved_354;
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uint32_t reserved_358;
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uint32_t reserved_35c;
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uint32_t reserved_360;
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uint32_t reserved_364;
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uint32_t reserved_368;
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uint32_t reserved_36c;
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uint32_t reserved_370;
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uint32_t reserved_374;
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uint32_t reserved_378;
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uint32_t reserved_37c;
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uint32_t reserved_380;
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uint32_t reserved_384;
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uint32_t reserved_388;
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uint32_t reserved_38c;
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uint32_t reserved_390;
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uint32_t reserved_394;
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uint32_t reserved_398;
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uint32_t reserved_39c;
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uint32_t reserved_3a0;
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uint32_t reserved_3a4;
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uint32_t reserved_3a8;
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uint32_t reserved_3ac;
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uint32_t reserved_3b0;
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uint32_t reserved_3b4;
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uint32_t reserved_3b8;
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uint32_t reserved_3bc;
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uint32_t reserved_3c0;
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uint32_t reserved_3c4;
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uint32_t reserved_3c8;
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uint32_t reserved_3cc;
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uint32_t reserved_3d0;
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uint32_t reserved_3d4;
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uint32_t reserved_3d8;
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uint32_t reserved_3dc;
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uint32_t reserved_3e0;
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uint32_t reserved_3e4;
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uint32_t reserved_3e8;
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uint32_t reserved_3ec;
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uint32_t reserved_3f0;
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uint32_t reserved_3f4;
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uint32_t reserved_3f8;
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uint32_t apb_ctrl_date; /**/
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} apb_saradc_dev_t;
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extern apb_saradc_dev_t APB_SARADC;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_APB_SARADC_STRUCT_H_ */
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