mirror of
https://github.com/espressif/esp-idf.git
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112 lines
3.7 KiB
C
112 lines
3.7 KiB
C
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_intr_alloc.h"
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#include "esp_debug_helpers.h"
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#include "soc/periph_defs.h"
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#include "soc/system_reg.h"
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#include "hal/cpu_hal.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/portmacro.h"
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#define REASON_YIELD BIT(0)
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#define REASON_FREQ_SWITCH BIT(1)
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#define REASON_PRINT_BACKTRACE BIT(2)
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static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
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static volatile uint32_t reason[portNUM_PROCESSORS];
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static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
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{
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portYIELD_FROM_ISR();
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}
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static void IRAM_ATTR esp_crosscore_isr(void *arg)
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{
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uint32_t my_reason_val;
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//A pointer to the correct reason array item is passed to this ISR.
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volatile uint32_t *my_reason = arg;
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//Clear the interrupt first.
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if (cpu_hal_get_core_id() == 0) {
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
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} else {
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0);
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}
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//Grab the reason and clear it.
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portENTER_CRITICAL_ISR(&reason_spinlock);
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my_reason_val = *my_reason;
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*my_reason = 0;
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portEXIT_CRITICAL_ISR(&reason_spinlock);
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//Check what we need to do.
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if (my_reason_val & REASON_YIELD) {
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esp_crosscore_isr_handle_yield();
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}
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if (my_reason_val & REASON_FREQ_SWITCH) {
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/* Nothing to do here; the frequency switch event was already
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* handled by a hook in xtensa_vectors.S. Could be used in the future
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* to allow DFS features without the extra latency of the ISR hook.
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*/
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}
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if (my_reason_val & REASON_PRINT_BACKTRACE) {
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esp_backtrace_print(100);
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}
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}
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// Initialize the crosscore interrupt on this core.
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void esp_crosscore_int_init(void)
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{
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portENTER_CRITICAL(&reason_spinlock);
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reason[cpu_hal_get_core_id()] = 0;
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portEXIT_CRITICAL(&reason_spinlock);
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if (cpu_hal_get_core_id() == 0) {
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ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void *)&reason[0], NULL));
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} else {
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ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void *)&reason[1], NULL));
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}
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}
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static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
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{
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assert(core_id < portNUM_PROCESSORS);
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//Mark the reason we interrupt the other CPU
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portENTER_CRITICAL(&reason_spinlock);
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reason[core_id] |= reason_mask;
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portEXIT_CRITICAL(&reason_spinlock);
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//Poke the other CPU.
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if (core_id == 0) {
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
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} else {
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1);
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}
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}
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void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
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{
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esp_crosscore_int_send(core_id, REASON_YIELD);
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}
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void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
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{
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esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
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}
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void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
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{
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esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
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}
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