Ivan Grokhotkov b4939b1121 bootloader, esp32: add workaround for Tensilica erratum 572 ... If zero-overhead loop buffer is enabled, under certain rare conditions when executing a zero-overhead loop, the CPU may attempt to execute an invalid instruction. Work around by disabling the buffer.		2019-01-23 16:23:08 +08:00
..
include/soc	bootloader, esp32: add workaround for Tensilica erratum 572	2019-01-23 16:23:08 +08:00
test	ci: Only run XTAL unit tests assuming board has an XTAL, run less repeats	2018-05-15 15:43:24 +08:00
cpu_util.c	esp_restart: fix possible race while stalling other CPU, enable WDT early	2017-10-26 19:53:53 +08:00
gpio_periph.c	soc: Fix check_long_hold_gpio and move def to soc	2018-06-26 12:47:55 +05:00
i2c_apll.h	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
i2c_bbpll.h	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
i2c_rtc_clk.h	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
rtc_clk.c	soc/rtc: reset BBPLL configuration after enabling it	2018-12-21 13:38:22 +08:00
rtc_init.c	soc: rtc_vddsdio_get_config() In default configuration, VDD_SDIO LDO is always enabled	2018-05-25 15:14:13 +10:00
rtc_periph.c	Fix errors in rtc_gpio_desc values	2018-07-19 10:27:31 +03:00
rtc_pm.c	soc/rtc: don’t switch frequency in rtc_sleep_init	2018-04-26 18:52:45 +08:00
rtc_sleep.c	sleep: optimize light sleep wakeup latency	2018-04-26 19:36:47 +08:00
rtc_time.c	component/bt: implement bluetooth modem sleep mode, one mode for BLE only and another for dual mode bluetooth	2018-05-19 15:37:26 +08:00
soc_log.h	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
soc_memory_layout.c	Add logic to make external RAM usable with malloc()	2017-09-28 17:17:50 +08:00
sources.cmake	cmake: make main a component again	2018-09-13 11:13:27 +08:00
spi_periph.c	refactor(spi): move pin information into soc folder	2018-06-14 11:29:15 +08:00