mirror of
https://github.com/espressif/esp-idf.git
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114 lines
3.2 KiB
C
114 lines
3.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_attr.h"
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#include "hal/clk_tree_hal.h"
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#include "hal/clk_tree_ll.h"
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#include "hal/assert.h"
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#include "hal/log.h"
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static const char *CLK_HAL_TAG = "clk_hal";
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uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
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{
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switch (cpu_clk_src) {
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case SOC_CPU_CLK_SRC_XTAL:
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return clk_hal_xtal_get_freq_mhz();
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case SOC_CPU_CLK_SRC_CPLL:
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return clk_ll_cpll_get_freq_mhz(clk_hal_xtal_get_freq_mhz());
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case SOC_CPU_CLK_SRC_RC_FAST:
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return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
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default:
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// Unknown CPU_CLK mux input
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HAL_ASSERT(false);
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return 0;
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}
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}
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uint32_t clk_hal_cpu_get_freq_hz(void)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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uint32_t integer, numerator, denominator;
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clk_ll_cpu_get_divider(&integer, &numerator, &denominator);
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if (denominator == 0) {
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denominator = 1;
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numerator = 0;
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}
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return clk_hal_soc_root_get_freq_mhz(source) * MHZ * denominator / (integer * denominator + numerator);
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}
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static uint32_t clk_hal_mem_get_freq_hz(void)
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{
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return clk_hal_cpu_get_freq_hz() / clk_ll_mem_get_divider();
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}
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static uint32_t clk_hal_sys_get_freq_hz(void)
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{
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return clk_hal_mem_get_freq_hz() / clk_ll_sys_get_divider();
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}
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uint32_t clk_hal_apb_get_freq_hz(void)
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{
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return clk_hal_sys_get_freq_hz() / clk_ll_apb_get_divider();
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}
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uint32_t clk_hal_lp_slow_get_freq_hz(void)
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{
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switch (clk_ll_rtc_slow_get_src()) {
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case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
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return SOC_CLK_RC_SLOW_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
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return SOC_CLK_XTAL32K_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_RC32K:
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return SOC_CLK_RC32K_FREQ_APPROX;
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default:
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// Unknown RTC_SLOW_CLK mux input
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HAL_ASSERT(false);
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return 0;
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}
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}
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IRAM_ATTR uint32_t clk_hal_xtal_get_freq_mhz(void)
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{
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uint32_t freq = clk_ll_xtal_load_freq_mhz();
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if (freq == 0) {
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HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
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return (uint32_t)SOC_XTAL_FREQ_40M;
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}
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return freq;
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}
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uint32_t clk_hal_apll_get_freq_hz(void)
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{
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uint64_t xtal_freq_hz = (uint64_t)clk_hal_xtal_get_freq_mhz() * 1000000ULL;
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uint32_t o_div = 0;
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uint32_t sdm0 = 0;
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uint32_t sdm1 = 0;
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uint32_t sdm2 = 0;
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clk_ll_apll_get_config(&o_div, &sdm0, &sdm1, &sdm2);
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uint32_t numerator = ((4 + sdm2) << 16) | (sdm1 << 8) | sdm0;
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uint32_t denominator = (o_div + 2) << 17;
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uint32_t apll_freq_hz = (uint32_t)((xtal_freq_hz * numerator) / denominator);
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return apll_freq_hz;
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}
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void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
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{
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clk_ll_set_dbg_clk_ctrl(clk_sig, channel_id);
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clk_ll_set_dbg_clk_channel_divider(channel_id, 1);
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clk_ll_enable_dbg_clk_channel(channel_id, true);
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}
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void clk_hal_clock_output_set_divider(clock_out_channel_t channel_id, uint32_t div_num)
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{
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clk_ll_set_dbg_clk_channel_divider(channel_id, div_num);
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}
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void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
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{
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clk_ll_enable_dbg_clk_channel(channel_id, false);
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}
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