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d7ce04a5cd
* The RNG reading frequency of 200 KHz has been too high for C6 and H2 since on these chips the RNG output is combined with the RTC slow clock which is only 150KHz. Reduced the max reading frequency via esp_random() from 200KHz to 62.5KHz, which show best results in tests. Also updated the bootloader_fill_random() max frequency to the same value to be in line, even though it was just 83KHz.
107 lines
4.1 KiB
C
107 lines
4.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stddef.h>
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#include <string.h>
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#include <sys/param.h>
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#include "esp_attr.h"
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#include "esp_cpu.h"
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#include "soc/wdev_reg.h"
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#include "esp_private/esp_clk.h"
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#if defined CONFIG_IDF_TARGET_ESP32C6
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#include "hal/lp_timer_hal.h"
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#endif
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#if defined CONFIG_IDF_TARGET_ESP32S3
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#define APB_CYCLE_WAIT_NUM (1778) /* If APB clock is 80 MHz, the maximum sampling frequency is around 45 KHz*/
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/* 45 KHz reading frequency is the maximum we have tested so far on S3 */
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#elif defined CONFIG_IDF_TARGET_ESP32C6
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#define APB_CYCLE_WAIT_NUM (160 * 16) /* On ESP32C6, we only read one byte at a time, then XOR the value with
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* an asynchronous timer (see code below).
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* The current value translates to a sampling frequency of around 62.5 KHz
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* for reading 8 bit samples, which is the rate at which the RNG was tested,
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* plus additional overhead for the calculation, making it slower. */
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#elif defined CONFIG_IDF_TARGET_ESP32H2
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#define APB_CYCLE_WAIT_NUM (96 * 16) /* Same reasoning as for ESP32C6, but the CPU frequency on ESP32H2 is
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* 96MHz instead of 160 MHz */
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#else
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#define APB_CYCLE_WAIT_NUM (16)
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#endif
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#if defined CONFIG_IDF_TARGET_ESP32H2
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// TODO: temporary definition until IDF-6270 is implemented
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#include "soc/lp_timer_reg.h"
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static uint32_t IRAM_ATTR lp_timer_hal_get_cycle_count(void)
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{
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REG_SET_BIT(LP_TIMER_UPDATE_REG, LP_TIMER_MAIN_TIMER_UPDATE);
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uint32_t lo = REG_GET_FIELD(LP_TIMER_MAIN_BUF0_LOW_REG, LP_TIMER_MAIN_TIMER_BUF0_LOW);
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return lo;
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}
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#endif
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uint32_t IRAM_ATTR esp_random(void)
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{
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/* The PRNG which implements WDEV_RANDOM register gets 2 bits
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* of extra entropy from a hardware randomness source every APB clock cycle
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* (provided WiFi or BT are enabled). To make sure entropy is not drained
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* faster than it is added, this function needs to wait for at least 16 APB
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* clock cycles after reading previous word. This implementation may actually
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* wait a bit longer due to extra time spent in arithmetic and branch statements.
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*
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* As a (probably unncessary) precaution to avoid returning the
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* RNG state as-is, the result is XORed with additional
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* WDEV_RND_REG reads while waiting.
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*/
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/* This code does not run in a critical section, so CPU frequency switch may
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* happens while this code runs (this will not happen in the current
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* implementation, but possible in the future). However if that happens,
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* the number of cycles spent on frequency switching will certainly be more
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* than the number of cycles we need to wait here.
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*/
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uint32_t cpu_to_apb_freq_ratio = esp_clk_cpu_freq() / esp_clk_apb_freq();
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static uint32_t last_ccount = 0;
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uint32_t ccount;
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uint32_t result = 0;
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#if (defined CONFIG_IDF_TARGET_ESP32C6 || defined CONFIG_IDF_TARGET_ESP32H2)
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for (size_t i = 0; i < sizeof(result); i++) {
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do {
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ccount = esp_cpu_get_cycle_count();
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result ^= REG_READ(WDEV_RND_REG);
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} while (ccount - last_ccount < cpu_to_apb_freq_ratio * APB_CYCLE_WAIT_NUM);
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uint32_t current_rtc_timer_counter = (lp_timer_hal_get_cycle_count() & 0xFF);
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result ^= ((result ^ current_rtc_timer_counter) & 0xFF) << (i * 8);
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}
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#else
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do {
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ccount = esp_cpu_get_cycle_count();
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result ^= REG_READ(WDEV_RND_REG);
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} while (ccount - last_ccount < cpu_to_apb_freq_ratio * APB_CYCLE_WAIT_NUM);
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#endif
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last_ccount = ccount;
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return result ^ REG_READ(WDEV_RND_REG);
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}
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void esp_fill_random(void *buf, size_t len)
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{
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assert(buf != NULL);
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uint8_t *buf_bytes = (uint8_t *)buf;
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while (len > 0) {
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uint32_t word = esp_random();
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uint32_t to_copy = MIN(sizeof(word), len);
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memcpy(buf_bytes, &word, to_copy);
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buf_bytes += to_copy;
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len -= to_copy;
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}
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}
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