esp-idf/components/riscv
Darian Leung 61eb7baa6b esp_hw_support: Add esp_cpu.h abstraction and API
This commit updates the esp_cpu.h API. The new API presents a new
abstraction of the CPU where CPU presents the following interfaces:

- CPU Control (to stall/unstall/reset the CPU)
- CPU Registers (to read registers commonly used in SW such as SP, PC)
- CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts)
- Memory Port (to configure the CPU's memory bus for memory protection)
- Debugging (to configure/control the CPU's debugging port)

Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc
        builds for esp_cpu.h
2022-06-14 14:30:58 +08:00
..
include esp_hw_support: Add esp_cpu.h abstraction and API 2022-06-14 14:30:58 +08:00
CMakeLists.txt build-system: add property for architecture (riscv/xtensa) 2022-05-20 09:00:32 +08:00
instruction_decode.c interrupt: filter out reserved int number by decoding risc-v JAL instruction 2021-01-05 15:39:46 +08:00
interrupt.c esp_hw_support: Add esp_cpu.h abstraction and API 2022-06-14 14:30:58 +08:00
linker.lf arch: move stdatomic 2021-02-26 18:40:00 +08:00
project_include.cmake build system: removed target component 2022-05-24 09:12:59 +08:00
vectors.S riscv: Adds support for returning from exception handler 2022-02-24 08:55:40 +00:00