mirror of
https://github.com/espressif/esp-idf.git
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9b99fc9033
cpu retention: add riscv core sleep critical and non-critical register layout structure definition cpu retention: add assembly subroutine for cpu critical register backup and restore cpu retention: add cpu core critical register context backup and restore support cpu retention: add cpu core non-critical register context backup and restore support cpu retention: add interrupt priority register context backup and restore support cpu retention: add cache config register context backup and restore support cpu retention: add plic interrupt register context backup and restore support cpu retention: add clint interrupt register context backup and restore support cpu retention: wait icache state idle before pmu enter sleep
240 lines
7.5 KiB
ArmAsm
240 lines
7.5 KiB
ArmAsm
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/soc.h"
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#include "riscv/rvsleep-frames.h"
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#include "soc/soc_caps.h"
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#include "sdkconfig.h"
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#if !CONFIG_IDF_TARGET_ESP32C6
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#include "soc/lp_aon_reg.h"
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#include "soc/extmem_reg.h"
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#endif
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.section .data1,"aw"
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.global rv_core_critical_regs_frame
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.type rv_core_critical_regs_frame,@object
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.align 4
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rv_core_critical_regs_frame:
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.word 0
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/*
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--------------------------------------------------------------------------------
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This assembly subroutine is used to save the critical registers of the CPU
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core to the internal RAM before sleep, and modify the PMU control flag to
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indicate that the system needs to sleep. When the subroutine returns, it
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will return the memory pointer that saves the context information of the CPU
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critical registers.
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--------------------------------------------------------------------------------
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*/
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.section .iram1,"ax"
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.global rv_core_critical_regs_save
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.type rv_core_critical_regs_save,@function
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.align 4
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rv_core_critical_regs_save:
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/* arrived here in critical section. we need:
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save riscv core critical registers to RvCoreCriticalSleepFrame
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*/
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csrw mscratch, t0 /* use mscratch as temp storage */
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la t0, rv_core_critical_regs_frame
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lw t0, 0(t0) /* t0 pointer to RvCoreCriticalSleepFrame object */
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sw ra, RV_SLP_CTX_RA(t0)
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sw sp, RV_SLP_CTX_SP(t0)
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sw gp, RV_SLP_CTX_GP(t0)
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sw tp, RV_SLP_CTX_TP(t0)
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sw t1, RV_SLP_CTX_T1(t0)
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sw t2, RV_SLP_CTX_T2(t0)
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sw s0, RV_SLP_CTX_S0(t0)
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sw s1, RV_SLP_CTX_S1(t0)
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sw a0, RV_SLP_CTX_A0(t0)
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/* !! WARNING, do not use the a0 register below, a0 carries important sleep
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* information and will be returned as the return value !! */
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mv a0, t0
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sw a1, RV_SLP_CTX_A1(t0)
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sw a2, RV_SLP_CTX_A2(t0)
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sw a3, RV_SLP_CTX_A3(t0)
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sw a4, RV_SLP_CTX_A4(t0)
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sw a5, RV_SLP_CTX_A5(t0)
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sw a6, RV_SLP_CTX_A6(t0)
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sw a7, RV_SLP_CTX_A7(t0)
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sw s2, RV_SLP_CTX_S2(t0)
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sw s3, RV_SLP_CTX_S3(t0)
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sw s4, RV_SLP_CTX_S4(t0)
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sw s5, RV_SLP_CTX_S5(t0)
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sw s6, RV_SLP_CTX_S6(t0)
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sw s7, RV_SLP_CTX_S7(t0)
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sw s8, RV_SLP_CTX_S8(t0)
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sw s9, RV_SLP_CTX_S9(t0)
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sw s10, RV_SLP_CTX_S10(t0)
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sw s11, RV_SLP_CTX_S11(t0)
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sw t3, RV_SLP_CTX_T3(t0)
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sw t4, RV_SLP_CTX_T4(t0)
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sw t5, RV_SLP_CTX_T5(t0)
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sw t6, RV_SLP_CTX_T6(t0)
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csrr t1, mstatus
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sw t1, RV_SLP_CTX_MSTATUS(t0)
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csrr t2, mtvec
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sw t2, RV_SLP_CTX_MTVEC(t0)
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csrr t3, mcause
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sw t3, RV_SLP_CTX_MCAUSE(t0)
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csrr t1, mtval
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sw t1, RV_SLP_CTX_MTVAL(t0)
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csrr t2, mie
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sw t2, RV_SLP_CTX_MIE(t0)
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csrr t3, mip
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sw t3, RV_SLP_CTX_MIP(t0)
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csrr t1, mepc
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sw t1, RV_SLP_CTX_MEPC(t0)
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/*
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!!! Let idf knows it's going to sleep !!!
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RV_SLP_STK_PMUFUNC field is used to identify whether it is going to sleep or
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has just been awakened. We use the lowest 2 bits as indication information,
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3 means being awakened, 1 means going to sleep.
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*/
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li t1, ~0x3
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lw t2, RV_SLP_CTX_PMUFUNC(t0)
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and t2, t1, t2
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ori t2, t2, 0x1
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sw t2, RV_SLP_CTX_PMUFUNC(t0)
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mv t3, t0
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csrr t0, mscratch
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sw t0, RV_SLP_CTX_T0(t3)
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#if !CONFIG_IDF_TARGET_ESP32C6
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/* writeback dcache is required here!!! */
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la t0, EXTMEM_CACHE_SYNC_MAP_REG
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li t1, 0x10
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sw t1, 0x0(t0) /* set EXTMEM_CACHE_SYNC_MAP_REG bit 4 */
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la t2, EXTMEM_CACHE_SYNC_ADDR_REG
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sw zero, 0x0(t2) /* clear EXTMEM_CACHE_SYNC_ADDR_REG */
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la t0, EXTMEM_CACHE_SYNC_SIZE_REG
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sw zero, 0x0(t0) /* clear EXTMEM_CACHE_SYNC_SIZE_REG */
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la t1, EXTMEM_CACHE_SYNC_CTRL_REG
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lw t2, 0x0(t1)
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ori t2, t2, 0x4
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sw t2, 0x0(t1)
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li t0, 0x10 /* SYNC_DONE bit */
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wait_sync_done:
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lw t2, 0x0(t1)
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and t2, t0, t2
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beqz t2, wait_sync_done
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#endif
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lw t0, RV_SLP_CTX_T0(t3)
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lw t1, RV_SLP_CTX_T1(t3)
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lw t2, RV_SLP_CTX_T2(t3)
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lw t3, RV_SLP_CTX_T3(t3)
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ret
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.size rv_core_critical_regs_save, . - rv_core_critical_regs_save
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#define CSR_PCER_U 0x800
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#define CSR_PCMR_U 0x801
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#define PCER_CYCLES (1<<0) /* count clock cycles */
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#define PCMR_GLOBAL_EN (1<<0) /* enable count */
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#define pcer CSR_PCER_U
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#define pcmr CSR_PCMR_U
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/*
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--------------------------------------------------------------------------------
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This assembly subroutine is used to restore the CPU core critical register
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context before sleep after system wakes up, modify the PMU control
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information, and return the critical register context memory object pointer.
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After the subroutine returns, continue to restore other modules of the
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system.
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--------------------------------------------------------------------------------
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*/
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.section .iram1,"ax"
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.global rv_core_critical_regs_restore
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.type rv_core_critical_regs_restore,@function
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.align 4
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rv_core_critical_regs_restore:
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la t0, rv_core_critical_regs_frame
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lw t0, 0(t0) /* t0 pointer to RvCoreCriticalSleepFrame object */
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beqz t0, .skip_restore /* make sure we do not jump to zero address */
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/*
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!!! Let idf knows it's sleep awake. !!!
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RV_SLP_STK_PMUFUNC field is used to identify whether it is going to sleep or
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has just been awakened. We use the lowest 2 bits as indication information,
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3 means being awakened, 1 means going to sleep.
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*/
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lw t1, RV_SLP_CTX_PMUFUNC(t0)
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ori t1, t1, 0x3
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sw t1, RV_SLP_CTX_PMUFUNC(t0)
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lw t2, RV_SLP_CTX_MEPC(t0)
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csrw mepc, t2
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lw t3, RV_SLP_CTX_MIP(t0)
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csrw mip, t3
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lw t1, RV_SLP_CTX_MIE(t0)
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csrw mie, t1
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lw t2, RV_SLP_CTX_MSTATUS(t0)
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csrw mstatus, t2
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lw t3, RV_SLP_CTX_MTVEC(t0)
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csrw mtvec, t3
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lw t1, RV_SLP_CTX_MCAUSE(t0)
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csrw mcause, t1
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lw t2, RV_SLP_CTX_MTVAL(t0)
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csrw mtval, t2
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lw t6, RV_SLP_CTX_T6(t0)
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lw t5, RV_SLP_CTX_T5(t0)
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lw t4, RV_SLP_CTX_T4(t0)
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lw t3, RV_SLP_CTX_T3(t0)
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lw s11, RV_SLP_CTX_S11(t0)
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lw s10, RV_SLP_CTX_S10(t0)
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lw s9, RV_SLP_CTX_S9(t0)
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lw s8, RV_SLP_CTX_S8(t0)
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lw s7, RV_SLP_CTX_S7(t0)
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lw s6, RV_SLP_CTX_S6(t0)
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lw s5, RV_SLP_CTX_S5(t0)
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lw s4, RV_SLP_CTX_S4(t0)
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lw s3, RV_SLP_CTX_S3(t0)
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lw s2, RV_SLP_CTX_S2(t0)
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lw a7, RV_SLP_CTX_A7(t0)
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lw a6, RV_SLP_CTX_A6(t0)
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lw a5, RV_SLP_CTX_A5(t0)
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lw a4, RV_SLP_CTX_A4(t0)
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lw a3, RV_SLP_CTX_A3(t0)
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lw a2, RV_SLP_CTX_A2(t0)
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lw a1, RV_SLP_CTX_A1(t0)
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lw a0, RV_SLP_CTX_A0(t0)
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lw s1, RV_SLP_CTX_S1(t0)
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lw s0, RV_SLP_CTX_S0(t0)
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lw t2, RV_SLP_CTX_T2(t0)
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lw t1, RV_SLP_CTX_T1(t0)
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lw tp, RV_SLP_CTX_TP(t0)
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lw gp, RV_SLP_CTX_GP(t0)
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lw sp, RV_SLP_CTX_SP(t0)
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lw ra, RV_SLP_CTX_RA(t0)
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lw t0, RV_SLP_CTX_T0(t0)
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.skip_restore:
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ret
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.size rv_core_critical_regs_restore, . - rv_core_critical_regs_restore
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