mirror of
https://github.com/espressif/esp-idf.git
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2e826b7a8f
esp_system: removed repeated interrupt allocator code and moved common code to esp_system xtens: moved xtensa specific code from freertos to the xtensa component hal/interrupt_controller: added interrupt controller hal and ll files docs: update the doxyfile with new location of esp_itr_alloc.h file xtensa: fixed dangerous relocation problem after moving xtensa interrupt files out of freertos docs: removed Xtensa reference from intr_allocator api-reference xtensa: pushed the interrupt function that manages non iram interrupts to the xtensa layer esp_system/test: fixed platform dependent setting for intr_allocator tests hal: rename the functions used to manage non iram interrupt mask.
171 lines
5.0 KiB
C
171 lines
5.0 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdbool.h>
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#include "hal/interrupt_controller_types.h"
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#include "hal/interrupt_controller_ll.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Gets target platform interrupt descriptor table
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*
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* @return Address of interrupt descriptor table
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*/
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__attribute__((pure)) const int_desc_t *interrupt_controller_hal_desc_table(void);
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/**
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* @brief Gets the interrupt type given an interrupt number.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @return interrupt type
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*/
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__attribute__((pure)) int_type_t interrupt_controller_hal_desc_type(int interrupt_number);
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/**
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* @brief Gets the interrupt level given an interrupt number.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @return interrupt level bitmask
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*/
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__attribute__((pure)) int interrupt_controller_hal_desc_level(int interrupt_number);
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/**
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* @brief Gets the cpu flags given the interrupt number and target cpu.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @param cpu_number CPU number between 0 and SOC_CPU_CORES_NUM - 1
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* @return flags for that interrupt number
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*/
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__attribute__((pure)) uint32_t interrupt_controller_hal_desc_flags(int interrupt_number, int cpu_number);
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/**
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* @brief Gets the interrupt type given an interrupt number.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @return interrupt type
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*/
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static inline int_type_t interrupt_controller_hal_get_type(int interrupt_number)
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{
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return interrupt_controller_hal_desc_type(interrupt_number);
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}
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/**
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* @brief Gets the interrupt level given an interrupt number.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @return interrupt level bitmask
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*/
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static inline int interrupt_controller_hal_get_level(int interrupt_number)
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{
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return interrupt_controller_hal_desc_level(interrupt_number);
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}
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/**
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* @brief Gets the cpu flags given the interrupt number and target cpu.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @param cpu_number CPU number between 0 and SOC_CPU_CORES_NUM - 1
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* @return flags for that interrupt number
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*/
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static inline uint32_t interrupt_controller_hal_get_cpu_desc_flags(int interrupt_number, int cpu_number)
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{
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return interrupt_controller_hal_desc_flags(interrupt_number, cpu_number);
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}
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/**
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* @brief enable interrupts specified by the mask
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*
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* @param mask bitmask of interrupts that needs to be enabled
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*/
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static inline void interrupt_controller_hal_enable_interrupts(uint32_t mask)
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{
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intr_cntrl_ll_enable_interrupts(mask);
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}
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/**
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* @brief disable interrupts specified by the mask
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*
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* @param mask bitmask of interrupts that needs to be disabled
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*/
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static inline void interrupt_controller_hal_disable_interrupts(uint32_t mask)
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{
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intr_cntrl_ll_disable_interrupts(mask);
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}
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/**
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* @brief checks if given interrupt number has a valid handler
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*
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* @param intr interrupt number ranged from 0 to 31
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* @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1
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* @return true for valid handler, false otherwise
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*/
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static inline bool interrupt_controller_hal_has_handler(int intr, int cpu)
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{
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return intr_cntrl_ll_has_handler(intr, cpu);
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}
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/**
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* @brief sets interrupt handler and optional argument of a given interrupt number
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*
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* @param intr interrupt number ranged from 0 to 31
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* @param handler handler invoked when an interrupt occurs
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* @param arg optional argument to pass to the handler
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*/
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static inline void interrupt_controller_hal_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg)
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{
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intr_cntrl_ll_set_int_handler(intr, handler, arg);
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}
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/**
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* @brief Gets argument passed to handler of a given interrupt number
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*
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* @param intr interrupt number ranged from 0 to 31
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*
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* @return argument used by handler of passed interrupt number
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*/
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static inline void * interrupt_controller_hal_get_int_handler_arg(uint8_t intr)
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{
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return intr_cntrl_ll_get_int_handler_arg(intr);
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}
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/**
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* @brief Disables interrupts that are not located in iram
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*
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* @param newmask mask of interrupts needs to be disabled
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* @return oldmask where to store old interrupts state
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*/
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static inline uint32_t interrupt_controller_hal_disable_int_mask(uint32_t newmask)
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{
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return intr_cntrl_ll_disable_int_mask(newmask);
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}
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/**
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* @brief Enables interrupts that are not located in iram
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*
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* @param newmask mask of interrupts needs to be disabled
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*/
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static inline void interrupt_controller_hal_enable_int_mask(uint32_t newmask)
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{
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intr_cntrl_ll_enable_int_mask(newmask);
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}
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#ifdef __cplusplus
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}
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#endif
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